Synthesis and STA Training with hands on project

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Synthesis and STA Training

Course Duration : 15 weeks

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About Course

Synthesis Training covers the aspect of converting the design in form of RTL into Technology mapped netlist. Synthesis is an algorithm intensive task consisting of many stages within it requiring various inputs in order to produce a functionally correct netlist. The main part of Synthesis Training consists of reading in the design, converting RTL to Boolean equations through elaboration, then converting the Boolean equations to Generic Mapped Cells and then technology mapped cells from library, setting constraints, optimizing the design, analyzing the results and saving the design database for Placement and Routing stage to take on. Candidates who are interested in exploring opportunities in Synthesis and Front-end STA can undergo this in-depth Synthesis training to get good understanding of RTL constructs, Gate level Netlist, Constraint Development, Latch based designs, pipe lining and re-timing, basic Scan stitching, Setup timing closure, Topography based logic re-structuring, Wire Load Models, Logical Equivalence Checks. Hierarchical Synthesis is another key feature covered in this Synthesis Training Cadence Implementation Suite for Synthesis (as RTL Compiler / Genus) would be used in this Synthesis Training program. Candidates would get hands on work on two full designs.


... Synthesis Training Topic covered.
Introduction to synthesis.
Reading RTL in HDL form, dotlibs, SDC
Different types of RTL constructs
Analyzing dotlib files
Elaboration and Generic Synthesis
Understanding DesignWare components and Logical Operators
Clock gating insertion for reducing Dynamic power post CTS
Creating list of dont_touch and dont_use cells
Technology mapped Synthesis and optimization
Scan Insertion techniques
Checking Design for number of instances, area estimate
Check clock reaching clock pins of flops, unclocked flops
Time borrowing concepts for latch based paths
Leakage variants of standard cells LVT, RVT, HVT
Constraints on logical hierarchy boundaries
Setting Max Transition, Max Capacitance, Max Fanout
Push down and pull up timing constraints
Master clocks and generated clocks in design
Estimating uncertainty values, input and output delays in SDC
False path, Multi cycle path exceptions.
Disabling timing loops in design
Logical Equivalence Checking fundamentals (Top level and Hierarchical)
Hand off database to PnR

Curriculum

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Introduction to synthesis.
HDL Modeling
Synthesis flow
Constraining the design for timing, area, power
Synthesize the Design
Analyze & Debug the results .
Optimization techniques
Report generation
Save the results and generate interface files to other tools
Introduction to synthesis.
HDL Modeling
Synthesis flow
Constraining the design for timing, area, power
Synthesize the Design
Analyze & Debug the results .
Optimization techniques
Report generation
Save the results and generate interface files to other tools
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Introduction to Static Timing Analysis
Understanding Delays & Libraries:
Constraining the design with SDC commands.
Timing Analysis of Different Paths
Analyzing Timing Reports
Timing Exceptions:
Operating Conditions
Check timing by loading different .libs
Post Layout STA:
Multi-Mode Multi-Corner Analysis (MMMC)
Cross Talk (SI) Analysis
Sign-off STA & ECO Flow
Practical STA Issues and Solutions

Course videos

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Unit 1 STA SES1 01:27:52
Unit 2 STA SES2 01:57:52
Unit 3 STA SES3 01:37:15
Unit 4 STA SES4 02:14:14
Unit 5 STA SES5 01:57:18
Unit 6 STA SES6 01:55:32
Unit 7 STA SES7 02:24:22
Unit 8 STA SES8 02:04:05
Unit 9 STA SES9 02:26:54
Unit 10 STA SES10 01:58:38
Unit 11 STA SES11 02:38:42
Unit 12 STA SES12 02:30:28
Unit 13 STA SES13 02:18:10
Unit 14 STA SES14 01:25:14
Unit 15 STA SES15 02:23:05
Unit 16 STA SES16 01:53:29
Unit 17 STA SES17 01:23:38
Unit 18 STA LAB SES1 00:29:23
Unit 19 STA LAB SES2 01:24:34
Unit 20 STA LAB SES3 02:52:16
Unit 21 STA LAB SES4 01:56:36
Unit 22 STA LAB SES5 01:47:37
Unit 23 STA LAB SES6 00:58:52
Unit 24 STA Constraints#1 03:39:50
Unit 25 STA Constraints#2 03:29:54
Unit 26 STA Constraints#3 04:05:42
Unit 27 STA Constraints#4 03:29:04
Unit 28 STA Constraints#5 03:23:18
Unit 29 STA Constraints#603:28:23
Unit 30 STA Constraints#7 03:13:14
Unit 31 PD Basics Intro Synthesis part1 00:36:46
Unit 32 PD Basics Intro Synthesis part2 00:32:01
Unit 33 Synthesis ses3 01:54:34
Unit 34 Synthesis ses4 03:22:01
Unit 35 PD Ses SB Synthesis ses5 04:58:57
Unit 36 PD Ses SB Synthesis ses6 05:30:58
Unit 37 synthesis ses7 01:18:30
Unit 38 synthesis ses8 01:03:11
Unit 39 synthesis ses9 01:40:23
Unit 40 synthesis ses10 02:53:01
Unit 41 synthesis ses11 03:21:33
Unit 42 synthesis ses12 02:39:25


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