{"id":8047,"date":"2025-10-22T11:47:56","date_gmt":"2025-10-22T11:47:56","guid":{"rendered":"https:\/\/inskill.in\/training\/digital-design-copy\/"},"modified":"2026-10-23T06:28:00","modified_gmt":"2026-10-23T06:28:00","slug":"dft-training","status":"publish","type":"page","link":"https:\/\/inskill.in\/training\/dft-training\/","title":{"rendered":"DFT Training"},"content":{"rendered":"\t\t
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DFT Training<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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DFT Training<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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        • \n \n \n About Course<\/span> \n <\/li>\n
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        • \n \n \n Course Videos<\/span> \n <\/li>\n
        • \n \n \n Course Curriculum<\/span> \n <\/li>\n
        • \n \n \n Benefits of eLearning?<\/span> \n <\/li>\n
        • \n \n \n Course Instructor<\/span> \n <\/li>\n \n <\/ul>\n <\/div>\n \n
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          About Course<\/h5>

          DFT Training \u2013 Design for Testability Course (Scan, ATPG, JTAG, MBIST)<\/h2>

          Design for Testability (DFT)<\/strong> involves using advanced test techniques such as Scan, ATPG, JTAG, MBIST, LBIST and Test Compression<\/strong> to improve hardware testability. These techniques are essential for identifying manufacturing defects like stuck-at faults, transition delay faults, path delay faults<\/strong>, and other structural defects in ASIC and SoC designs.<\/p>

          This industry-oriented DFT Training course<\/strong> is designed to provide in-depth exposure to complete DFT flow, Scan architecture, ATPG pattern generation, Debug methodologies, and Diagnosis techniques<\/strong> used in semiconductor companies.<\/p>

          What You Will Learn in DFT Training<\/h3>
          • DFT fundamentals and testability concepts<\/li>
          • Different fault models: Stuck-at, Transition Delay, Path Delay faults<\/li>
          • SoC Scan Architecture and various Scan types<\/li>
          • Scan insertion and Hierarchical Scan Design<\/li>
          • ATPG DRC Debug and ATPG Simulation Debug<\/li>
          • Test Compression techniques (TestKompress)<\/li>
          • DFT Diagnosis methodologies<\/li>
          • JTAG (Boundary Scan) architecture and applications<\/li>
          • Memory BIST (MBIST) and Logic BIST (LBIST)<\/li><\/ul>

            Hands-On DFT Practical Training<\/h3>

            As part of the training, students will work on a complex SoC design example<\/strong> with multiple embedded memories. Practical sessions include:<\/p>

            • Scan chain insertion and validation<\/li>
            • MBIST controller integration and memory testing<\/li>
            • Boundary Scan (JTAG) implementation<\/li>
            • ATPG pattern generation for different fault models<\/li>
            • Test pattern compression using TestKompress<\/li>
            • Pattern validation through simulations<\/li><\/ul>

              Compressed test patterns reduce IO usage, minimize tester memory requirements, and improve production test efficiency.<\/p>

              Tool-Based Training \u2013 Mentor Graphics Tessent<\/h3>

              The course uses Mentor Graphics Tessent Tool<\/strong>, one of the most widely adopted DFT tools in the semiconductor industry. Industry surveys indicate that Tessent is used by more than 80% of leading semiconductor companies.<\/p>

              Students will gain practical exposure to:<\/p>

              • Scan insertion using Tessent<\/li>
              • ATPG pattern generation and coverage analysis<\/li>
              • ATPG debug and fault simulation<\/li>
              • Compression setup and validation<\/li><\/ul>

                Students will have access to the Tessent tool at the institute for 12 months after course completion, with an option to extend access.<\/p>

                Who Should Enroll?<\/h3>
                • VLSI freshers aiming for DFT Engineer roles<\/li>
                • RTL Design engineers transitioning to DFT<\/li>
                • Verification engineers exploring Test Engineering<\/li>
                • Working professionals upgrading DFT tool skills<\/li><\/ul>

                  This DFT Training ensures strong conceptual clarity, extensive hands-on experience, and industry-ready expertise in Scan, ATPG, JTAG, MBIST, and Test Compression methodologies.<\/p><\/div><\/div> <\/div>\n\t\t \n

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                  Demo Videos<\/h5>\n