{"id":9087,"date":"2026-02-16T10:33:23","date_gmt":"2026-02-16T10:33:23","guid":{"rendered":"https:\/\/inskill.in\/training\/advanced-physical-design-training-copy\/"},"modified":"2026-03-31T07:08:20","modified_gmt":"2026-03-31T07:08:20","slug":"physical-design-training","status":"publish","type":"page","link":"https:\/\/inskill.in\/training\/physical-design-training\/","title":{"rendered":"Physical design training"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"9087\" class=\"elementor elementor-9087\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-c32f84d elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"c32f84d\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-8ab2f2a\" data-id=\"8ab2f2a\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-bf06656 elementor-widget elementor-widget-heading\" data-id=\"bf06656\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h2 class=\"elementor-heading-title elementor-size-default\">physical design training<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-50c5ef1 elementor-widget elementor-widget-heading\" data-id=\"50c5ef1\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Home > \nCourse<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-b6b5a0f elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"b6b5a0f\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-13f4440\" data-id=\"13f4440\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-94547bc elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"94547bc\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-inner-column elementor-element elementor-element-7bcfa7c\" data-id=\"7bcfa7c\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-7452ca1 elementor-widget elementor-widget-heading\" data-id=\"7452ca1\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">physical design training<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5101cb3 elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"5101cb3\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<link rel=\"stylesheet\" href=\"https:\/\/inskill.in\/training\/wp-content\/plugins\/elementor\/assets\/css\/widget-icon-list.min.css\">\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-calendar-alt\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Course Duration: 131 Hours<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5dc06f7 elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"5dc06f7\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul 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fa-user-tag\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">3000 (Student Enrolled till Now)<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-d25cf2d elementor-widget elementor-widget-eael-adv-tabs\" data-id=\"d25cf2d\" data-element_type=\"widget\" data-widget_type=\"eael-adv-tabs.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t        <div id=\"eael-advance-tabs-d25cf2d\" class=\"eael-advance-tabs eael-tabs-horizontal eael-tab-auto-active\" data-tabid=\"d25cf2d\">\n            <div class=\"eael-tabs-nav\">\n                <ul class=\"eael-tab-inline-icon\">\n                                            <li id=\"about-course\" class=\"active-default eael-tab-item-trigger\" aria-selected=\"true\" data-tab=\"1\" role=\"tab\" tabindex=\"0\" aria-controls=\"about-course-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">About Course<\/span>                            \n                                                    <\/li>\n                                            <li id=\"demo-videos\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"2\" role=\"tab\" tabindex=\"-1\" aria-controls=\"demo-videos-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Demo Videos<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-videos\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"3\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-videos-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Videos<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-curriculum\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"4\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-curriculum-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Curriculum<\/span>                            \n                                                    <\/li>\n                                            <li id=\"benefits-of-elearning\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"5\" role=\"tab\" tabindex=\"-1\" aria-controls=\"benefits-of-elearning-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Benefits of eLearning?<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-instructor\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"6\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-instructor-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Instructor<\/span>                            \n                                                    <\/li>\n                                    <\/ul>\n            <\/div>\n            \n            <div class=\"eael-tabs-content\">\n\t\t        \n                    <div id=\"about-course-tab\" class=\"clearfix eael-tab-content-item active-default\" data-title-link=\"about-course-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">About Course<\/h5><div class=\"course-list\"><div style=\"font-family: 'Segoe UI', Roboto, Arial, sans-serif; line-height: 1.9; color: #333; max-width: 1000px; margin: auto;\"><h2 style=\"font-size: 30px; font-weight: bold; color: #0a2a66; margin-bottom: 15px;\">VLSI Physical Design Training \u2013 Complete ASIC Backend Implementation Course<\/h2><p style=\"font-size: 16px; margin-bottom: 15px;\">This <strong>8-month Physical Design training program<\/strong> is a comprehensive, industry-oriented course designed to build strong fundamentals and advanced expertise in <strong>VLSI Backend Implementation<\/strong>. The program covers the complete <strong>ASIC Physical Design flow from Netlist to GDSII<\/strong> with hands-on exposure to real-time projects at <strong>14nm technology node<\/strong>.<\/p><p style=\"font-size: 16px; margin-bottom: 15px;\">The course is structured to prepare freshers, final-year students, and working professionals for careers in <strong>Physical Design, ASIC Backend Engineering, Timing Analysis, and Chip Implementation<\/strong> roles in semiconductor companies.<\/p><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Course Duration &amp; Structure<\/h3><p style=\"font-size: 16px; margin-bottom: 10px;\"><strong>Foundation Phase \u2013 2.5 Months<\/strong><br \/>Digital Design &amp; Physical Design Fundamentals<\/p><p style=\"font-size: 16px; margin-bottom: 10px;\"><strong>Advanced Phase \u2013 5.5 Months<\/strong><br \/>Advanced Backend Implementation with Real-Time Projects<\/p><p style=\"font-size: 16px; margin-bottom: 15px;\">Total Duration: <strong>8 Months Intensive Industry Training<\/strong><\/p><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Foundation Training \u2013 Digital &amp; Backend Fundamentals<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Digital Design fundamentals (Combinational &amp; Sequential logic)<\/li><li>CMOS basics and semiconductor concepts<\/li><li>ASIC Design Flow overview<\/li><li>Introduction to Physical Design stages<\/li><li>Understanding Netlist to GDSII flow<\/li><li>Linux basics for VLSI engineers<\/li><li>TCL scripting fundamentals<\/li><li>Static Timing Analysis (STA) basics<\/li><\/ul><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Advanced Physical Design Implementation<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Floorplanning and Block-Level Planning strategies<\/li><li>Power Planning and Power Grid Design<\/li><li>Standard Cell Placement and Optimization<\/li><li>Clock Tree Synthesis (CTS) and Clock Optimization<\/li><li>Global &amp; Detailed Routing strategies<\/li><li>Congestion Analysis and Routing Debug<\/li><li>Setup and Hold Violation Debugging<\/li><li>Timing Closure Techniques<\/li><li>Multi-Corner Multi-Mode (MCMM) timing analysis<\/li><li>IR Drop and Electromigration (EM) awareness<\/li><li>Physical Verification basics (DRC \/ LVS concepts)<\/li><li>Low Power Design Implementation overview<\/li><li>Signoff Flow understanding before Tapeout<\/li><\/ul><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Industry Tools Exposure<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Synopsys ICC2 \u2013 Complete Physical Design Implementation Flow<\/li><li>Cadence Innovus \u2013 Block &amp; Full-Chip Backend Implementation<\/li><li>PrimeTime \u2013 Static Timing Analysis and Timing Signoff<\/li><li>Debugging real-time timing violations and optimization strategies<\/li><\/ul><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Hands-On Project Experience<\/h3><p style=\"font-size: 16px; margin-bottom: 15px;\">Students work on complete backend implementation projects at <strong>14nm technology node<\/strong>, covering the full Physical Design cycle:<\/p><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Block-Level Physical Design Project<\/li><li>Timing Closure Project<\/li><li>Full flow implementation from Netlist to GDSII<\/li><li>Real-time routing and timing debug scenarios<\/li><\/ul><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Training Modes Available<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Classroom Training<\/li><li>Live Online Instructor-Led Training<\/li><li>Weekend Batches<\/li><li>Fast-Track Programs<\/li><li>Self-Paced E-Learning<\/li><\/ul><p style=\"font-size: 16px; margin-bottom: 15px;\">Flexible training options make this course suitable for both fresh graduates and working professionals without interrupting academic or job schedules.<\/p><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Who Should Enroll?<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>ECE \/ EEE Graduates<\/li><li>Final-Year Engineering Students<\/li><li>Freshers targeting Physical Design roles<\/li><li>RTL Engineers transitioning to Backend<\/li><li>Working Professionals upgrading ASIC implementation skills<\/li><\/ul><h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Career Opportunities After Completion<\/h3><ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\"><li>Physical Design Engineer<\/li><li>ASIC Backend Engineer<\/li><li>PD Implementation Engineer<\/li><li>Timing Engineer<\/li><li>STA Engineer<\/li><\/ul><p style=\"font-size: 16px; font-weight: 600; color: #0a2a66;\">This 8-month Physical Design training equips students with practical, tool-based backend expertise required by semiconductor and VLSI companies, ensuring strong career growth in ASIC and chip implementation domains.<\/p><\/div><\/div>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"demo-videos-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"demo-videos-tab\">\n\t\t\t\t        \t\t\t\t\t        <iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/2e1D2CnC_jE\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><span data-mce-type=\"bookmark\" style=\"display: inline-block; width: 0px; overflow: hidden; line-height: 0;\" class=\"mce_SELRES_start\">\ufeff<\/span><span data-mce-type=\"bookmark\" style=\"display: inline-block; width: 0px; overflow: hidden; line-height: 0;\" class=\"mce_SELRES_start\">\ufeff<\/span><span data-mce-type=\"bookmark\" style=\"display: inline-block; width: 0px; overflow: hidden; line-height: 0;\" class=\"mce_SELRES_start\">\ufeff<\/span><span data-mce-type=\"bookmark\" style=\"display: inline-block; width: 0px; overflow: hidden; line-height: 0;\" class=\"mce_SELRES_start\">\ufeff&lt;\/<iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/xvmFO85CooQ\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><span data-mce-type=\"bookmark\" style=\"display: inline-block; width: 0px; overflow: hidden; line-height: 0;\" class=\"mce_SELRES_start\">\ufeff<\/\n<iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/https:\/\/www.youtube.com\/watch?v=kHiHVy1aMa4\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/span><\/iframe>\n\n&nbsp;\n\n<iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/LJZqPnMVwYI\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe>\n\n<iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/U0uo_yPDVKs\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe>\n\n<iframe loading=\"lazy\" title=\"YouTube video player\" src=\"https:\/\/www.youtube.com\/embed\/BbXXaRrbg8E\" width=\"560\" height=\"315\" frameborder=\"0\" allowfullscreen=\"allowfullscreen\"><\/iframe>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-videos-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-videos-tab\">\n\t\t\t\t        \t\t\t\t\t        <table style=\"height: 5858px;\" width=\"604\"><tbody><tr><td width=\"46\">Unit Number<\/td><td width=\"256\">Topic<\/td><td width=\"84\">Duration(mins)<\/td><\/tr><tr><td width=\"46\">1<\/td><td width=\"256\">Introduction to digital system<\/td><td width=\"84\">24<\/td><\/tr><tr><td width=\"46\">2<\/td><td width=\"256\">Number system introduction and Radix conversion<\/td><td width=\"84\">60<\/td><\/tr><tr><td width=\"46\">3<\/td><td width=\"256\">Compliments of the number systems and 1 s and 2 s Compliments<\/td><td width=\"84\">92<\/td><\/tr><tr><td width=\"46\">4<\/td><td width=\"256\">9 s and 10 s Compliments, 7 s and 8 s Compliments and 15 s and 16 s Compliments<\/td><td width=\"84\">64<\/td><\/tr><tr><td width=\"46\">5<\/td><td width=\"256\">Gates and its truth table and Why NAND is preferred over NOR gate<\/td><td width=\"84\">71<\/td><\/tr><tr><td width=\"46\">6<\/td><td width=\"256\">NAND and NOR Realization<\/td><td width=\"84\">66<\/td><\/tr><tr><td width=\"46\">7<\/td><td width=\"256\">SOP and POS form, minterm, Maxterm canonical SOP and POS form<\/td><td width=\"84\">55<\/td><\/tr><tr><td width=\"46\">8<\/td><td width=\"256\">Boolean equations Switching equations<\/td><td width=\"84\">25<\/td><\/tr><tr><td width=\"46\">9<\/td><td width=\"256\">Boolean minimization techniques and K -map(2-variables,3-variables,4-variables) and Logisim tool introduction<\/td><td width=\"84\">99<\/td><\/tr><tr><td width=\"46\">10<\/td><td width=\"256\">Implicants, PI, EPT, NEPT and RPI<\/td><td width=\"84\">54<\/td><\/tr><tr><td width=\"46\">11<\/td><td width=\"256\">K -map(5-variables,6-variables)<\/td><td width=\"84\">25<\/td><\/tr><tr><td width=\"46\">12<\/td><td width=\"256\">K -map with don t care functions<\/td><td width=\"84\">26<\/td><\/tr><tr><td width=\"46\">13<\/td><td width=\"256\">Building of combinational logic circuits (code converters)<\/td><td width=\"84\">49<\/td><\/tr><tr><td width=\"46\">14<\/td><td width=\"256\">Code converters continues<\/td><td width=\"84\">43<\/td><\/tr><tr><td width=\"46\">15<\/td><td width=\"256\">Arithmetic circuits (HA, FA and Parallel Adder)<\/td><td width=\"84\">63<\/td><\/tr><tr><td width=\"46\">16<\/td><td width=\"256\">Subtractors using compliments (HS, FS)<\/td><td width=\"84\">61<\/td><\/tr><tr><td width=\"46\">17<\/td><td width=\"256\">MSI circuits (Multiplexers) and Gates using Muxs<\/td><td width=\"84\">66<\/td><\/tr><tr><td width=\"46\">18<\/td><td width=\"256\">Boolean function Implementation using Mux<\/td><td width=\"84\">53<\/td><\/tr><tr><td width=\"46\">19<\/td><td width=\"256\">FA using Mux and Mux tree<\/td><td width=\"84\">61<\/td><\/tr><tr><td width=\"46\">20<\/td><td width=\"256\">Demultiplexers<\/td><td width=\"84\">41<\/td><\/tr><tr><td width=\"46\">21<\/td><td width=\"256\">Decoders<\/td><td width=\"84\">40<\/td><\/tr><tr><td width=\"46\">22<\/td><td width=\"256\">Decoders configurations and priority encoders<\/td><td width=\"84\">71<\/td><\/tr><tr><td width=\"46\">23<\/td><td width=\"256\">Comparators<\/td><td width=\"84\">56<\/td><\/tr><tr><td width=\"46\">24<\/td><td width=\"256\">Introduction to sequential logic ckts, Basic storage element (NOR latch)<\/td><td width=\"84\">68<\/td><\/tr><tr><td width=\"46\">25<\/td><td width=\"256\">NAND latch<\/td><td width=\"84\">44<\/td><\/tr><tr><td width=\"46\">26<\/td><td width=\"256\">Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems<\/td><td width=\"84\">83<\/td><\/tr><tr><td width=\"46\">27<\/td><td width=\"256\">Master-Slave combination and Edge triggering Flip flops<\/td><td width=\"84\">78<\/td><\/tr><tr><td width=\"46\">28<\/td><td width=\"256\">Revision of latch, Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems<\/td><td width=\"84\">59<\/td><\/tr><tr><td width=\"46\">29<\/td><td width=\"256\">Master-Slave combination and its limitations<\/td><td width=\"84\">6<\/td><\/tr><tr><td width=\"46\">30<\/td><td width=\"256\">Edge triggering and its advantages<\/td><td width=\"84\">50<\/td><\/tr><tr><td width=\"46\">31<\/td><td width=\"256\">Asynchronous inputsOverriding inputs of Flip flops, Characteristic equations and Excitation table of Flip flops<\/td><td width=\"84\">64<\/td><\/tr><tr><td width=\"46\">32<\/td><td width=\"256\">Flip flop conversions<\/td><td width=\"84\">17<\/td><\/tr><tr><td width=\"46\">33<\/td><td width=\"256\">Applications of the Flip flops (Counters - Asynchronous up and down counters)<\/td><td width=\"84\">67<\/td><\/tr><tr><td width=\"46\">34<\/td><td width=\"256\">Asynchronous Mod-N counters<\/td><td width=\"84\">59<\/td><\/tr><tr><td width=\"46\">35<\/td><td width=\"256\">Asynchronous updown counters, Timing considerations of the flip flops and limitations of the Asynchronous counter<\/td><td width=\"84\">50<\/td><\/tr><tr><td width=\"46\">36<\/td><td width=\"256\">Design of synchronous counters<\/td><td width=\"84\">87<\/td><\/tr><tr><td width=\"46\">37<\/td><td width=\"256\">Registers, shift registers and its configurations, universal shift registers<\/td><td width=\"84\">62<\/td><\/tr><tr><td width=\"46\">38<\/td><td width=\"256\">Counters based on shift registers (Ring and Johnson counters)<\/td><td width=\"84\">51<\/td><\/tr><tr><td width=\"46\">39<\/td><td width=\"256\">Frequency divider circuits<\/td><td width=\"84\">100<\/td><\/tr><tr><td width=\"46\">40<\/td><td width=\"256\">Frequency multiplier and Edge detector circuits<\/td><td width=\"84\">35<\/td><\/tr><tr><td width=\"46\">41<\/td><td width=\"256\">Introduction to FSM, Implicit and Explicit FSM<\/td><td width=\"84\">62<\/td><\/tr><tr><td width=\"46\">42<\/td><td width=\"256\">FSM sequence detector of melay and moore model<\/td><td width=\"84\">101<\/td><\/tr><tr><td width=\"46\">43<\/td><td width=\"256\">Problems on FSM<\/td><td width=\"84\">81<\/td><\/tr><tr><td width=\"46\">44<\/td><td width=\"256\">Assignment discussion<\/td><td width=\"84\">33<\/td><\/tr><tr><td width=\"46\">45<\/td><td width=\"256\">Synchronizers to change the pipelining.<\/td><td width=\"84\">24<\/td><\/tr><tr><td width=\"46\">46<\/td><td width=\"256\">FSM<\/td><td width=\"84\">98<\/td><\/tr><tr><td width=\"46\">47<\/td><td width=\"256\">FSM-Mealy and moore problems,doubt discussion<\/td><td width=\"84\">101<\/td><\/tr><tr><td width=\"46\">48<\/td><td width=\"256\">D Flip flop using transmission gate<\/td><td width=\"84\">25<\/td><\/tr><tr><td width=\"46\">49<\/td><td width=\"256\">ASIC FLOW SES1<\/td><td width=\"84\">164<\/td><\/tr><tr><td width=\"46\">50<\/td><td width=\"256\">ASIC FLOW SES2<\/td><td width=\"84\">170<\/td><\/tr><tr><td width=\"46\">51<\/td><td width=\"256\">ASIC FLOW SES3<\/td><td width=\"84\">137<\/td><\/tr><tr><td width=\"46\">52<\/td><td width=\"256\">ASIC FLOW SES4<\/td><td width=\"84\">170<\/td><\/tr><tr><td width=\"46\">53<\/td><td width=\"256\">SES1 P1 Introduction to Linux and its applications<\/td><td width=\"84\">27<\/td><\/tr><tr><td width=\"46\">53<\/td><td width=\"256\">SES1 P2 Architecture of the Linux system<\/td><td width=\"84\">23<\/td><\/tr><tr><td width=\"46\">54<\/td><td width=\"256\">SES1 P3 Usage of the Cygwin<\/td><td width=\"84\">13<\/td><\/tr><tr><td width=\"46\">55<\/td><td width=\"256\">SES1 P4 File commands of the Linux system<\/td><td width=\"84\">63<\/td><\/tr><tr><td width=\"46\">56<\/td><td width=\"256\">SES2 P1-5 File commands continue<\/td><td width=\"84\">65<\/td><\/tr><tr><td width=\"46\">57<\/td><td width=\"256\">SES2 P2-6 File display and Miscellaneous commands<\/td><td width=\"84\">62<\/td><\/tr><tr><td width=\"46\">58<\/td><td width=\"256\">SES3 P1-7 file display and Miscellaneous commands continue<\/td><td width=\"84\">43<\/td><\/tr><tr><td width=\"46\">59<\/td><td width=\"256\">SES3 P2-8 Meta characters and regular expressions<\/td><td width=\"84\">42<\/td><\/tr><tr><td width=\"46\">60<\/td><td width=\"256\">SES4 P1-9 file compare commands<\/td><td width=\"84\">58<\/td><\/tr><tr><td width=\"46\">61<\/td><td width=\"256\">SES4 P1-10 .bashrc file<\/td><td width=\"84\">37<\/td><\/tr><tr><td width=\"46\">62<\/td><td width=\"256\">SES7 P1-11 piping, xargs and tee concept<\/td><td width=\"84\">41<\/td><\/tr><tr><td width=\"46\">63<\/td><td width=\"256\">SES7 P2-12 env variables, PS1, popd and pushd concept<\/td><td width=\"84\">33<\/td><\/tr><tr><td width=\"46\">64<\/td><td width=\"256\">SES7 P3-13 filters and commands<\/td><td width=\"84\">35<\/td><\/tr><tr><td width=\"46\">65<\/td><td width=\"256\">SES8 P1-14 Data manipulation(sed) commands<\/td><td width=\"84\">71<\/td><\/tr><tr><td width=\"46\">66<\/td><td width=\"256\">SES8 P1-15 Data manipulation(awk) commands<\/td><td width=\"84\">41<\/td><\/tr><tr><td width=\"46\">67<\/td><td width=\"256\">SES9 P1-16 File permission commands<\/td><td width=\"84\">69<\/td><\/tr><tr><td width=\"46\">68<\/td><td width=\"256\">SES9 P1-17 File compare commands<\/td><td width=\"84\">106<\/td><\/tr><tr><td width=\"46\">69<\/td><td width=\"256\">SES9 P1-18 Find commands<\/td><td width=\"84\">43<\/td><\/tr><tr><td width=\"46\">70<\/td><td width=\"256\">Introduction to TCL<\/td><td width=\"84\">39<\/td><\/tr><tr><td width=\"46\">71<\/td><td width=\"256\">How to run the TCL program<\/td><td width=\"84\">57<\/td><\/tr><tr><td width=\"46\">72<\/td><td width=\"256\">Formal syntax of the TCL<\/td><td width=\"84\">49<\/td><\/tr><tr><td width=\"46\">73<\/td><td width=\"256\">set, puts and gets commands<\/td><td width=\"84\">36<\/td><\/tr><tr><td width=\"46\">74<\/td><td width=\"256\">TCL Operators<\/td><td width=\"84\">86<\/td><\/tr><tr><td width=\"46\">75<\/td><td width=\"256\">TCL Control statements<\/td><td width=\"84\">58<\/td><\/tr><tr><td width=\"46\">76<\/td><td width=\"256\">TCL Control statements (if and for statements)<\/td><td width=\"84\">63<\/td><\/tr><tr><td width=\"46\">77<\/td><td width=\"256\">TCL Control statements (while statements)<\/td><td width=\"84\">31<\/td><\/tr><tr><td width=\"46\">78<\/td><td width=\"256\">TCL Control statements (switch and foreach statements)<\/td><td width=\"84\">29<\/td><\/tr><tr><td width=\"46\">79<\/td><td width=\"256\">TCL strings and its operators<\/td><td width=\"84\">23<\/td><\/tr><tr><td width=\"46\">80<\/td><td width=\"256\">Strings operators Conti...<\/td><td width=\"84\">67<\/td><\/tr><tr><td width=\"46\">81<\/td><td width=\"256\">Examples of Strings operators Conti...<\/td><td width=\"84\">63<\/td><\/tr><tr><td width=\"46\">82<\/td><td width=\"256\">Programs on TCL Strings operators<\/td><td width=\"84\">55<\/td><\/tr><tr><td width=\"46\">83<\/td><td width=\"256\">TCL Lists<\/td><td width=\"84\">25<\/td><\/tr><tr><td width=\"46\">84<\/td><td width=\"256\">Programs on TCL Lists<\/td><td width=\"84\">54<\/td><\/tr><tr><td width=\"46\">85<\/td><td width=\"256\">TCL special variables<\/td><td width=\"84\">60<\/td><\/tr><tr><td width=\"46\">86<\/td><td width=\"256\">Programs on TCL special variables<\/td><td width=\"84\">29<\/td><\/tr><tr><td width=\"46\">87<\/td><td width=\"256\">Programs on TCL special variables Conti...<\/td><td width=\"84\">34<\/td><\/tr><tr><td width=\"46\">88<\/td><td width=\"256\">TCL File handling operations<\/td><td width=\"84\">53<\/td><\/tr><tr><td width=\"46\">89<\/td><td width=\"256\">Programs on TCL File handling operations<\/td><td width=\"84\">58<\/td><\/tr><tr><td width=\"46\">90<\/td><td width=\"256\">Programs on TCL File handling operations Conti...<\/td><td width=\"84\">55<\/td><\/tr><tr><td width=\"46\">91<\/td><td width=\"256\">TCL Procedures and Programs on TCL Procedures<\/td><td width=\"84\">82<\/td><\/tr><tr><td width=\"46\">92<\/td><td width=\"256\">TCL Procedures and Programs on TCL Procedures Conti...<\/td><td width=\"84\">49<\/td><\/tr><tr><td width=\"46\">93<\/td><td width=\"256\">TCL Procedures and its parameters<\/td><td width=\"84\">51<\/td><\/tr><tr><td width=\"46\">94<\/td><td width=\"256\">TCL Arrays<\/td><td width=\"84\">31<\/td><\/tr><tr><td width=\"46\">95<\/td><td width=\"256\">TCL Associative Arrays<\/td><td width=\"84\">46<\/td><\/tr><tr><td width=\"46\">96<\/td><td width=\"256\">Programs on TCL Arrays<\/td><td width=\"84\">33<\/td><\/tr><tr><td width=\"46\">97<\/td><td width=\"256\">TCL Dictionary<\/td><td width=\"84\">64<\/td><\/tr><tr><td width=\"46\">98<\/td><td width=\"256\">TCL Regular expression<\/td><td width=\"84\">48<\/td><\/tr><tr><td width=\"46\">99<\/td><td width=\"256\">Programs on TCL Regular expression<\/td><td width=\"84\">47<\/td><\/tr><tr><td width=\"46\">100<\/td><td width=\"256\">Programs on TCL Regular expression Conti...<\/td><td width=\"84\">45<\/td><\/tr><tr><td width=\"46\">101<\/td><td width=\"256\">Programs on TCL Regular expression Conti...<\/td><td width=\"84\">60<\/td><\/tr><tr><td width=\"46\">102<\/td><td width=\"256\">Semiconductor Basics<\/td><td width=\"84\">52<\/td><\/tr><tr><td width=\"46\">103<\/td><td width=\"256\">Semiconductor Basics Part-2<\/td><td width=\"84\">6<\/td><\/tr><tr><td width=\"46\">104<\/td><td width=\"256\">Semiconductor Devices - Diodes<\/td><td width=\"84\">30<\/td><\/tr><tr><td width=\"46\">105<\/td><td width=\"256\">MOSFET operation &amp; Characteristics Part 1<\/td><td width=\"84\">78<\/td><\/tr><tr><td width=\"46\">106<\/td><td width=\"256\">MOSFET operation &amp; Characteristics Part 1--&gt;2<\/td><td width=\"84\">53<\/td><\/tr><tr><td width=\"46\">107<\/td><td width=\"256\">MOSFET operation &amp; Characteristics Part 2<\/td><td width=\"84\">76<\/td><\/tr><tr><td width=\"46\">108<\/td><td width=\"256\">MOSFET operation &amp; Characteristics Part 2--&gt;2<\/td><td width=\"84\">11<\/td><\/tr><tr><td width=\"46\">109<\/td><td width=\"256\">Pass transistors<\/td><td width=\"84\">45<\/td><\/tr><tr><td width=\"46\">110<\/td><td width=\"256\">pass transistor continuation<\/td><td width=\"84\">30<\/td><\/tr><tr><td width=\"46\">111<\/td><td width=\"256\">Pseudo NMOS<\/td><td width=\"84\">23<\/td><\/tr><tr><td width=\"46\">112<\/td><td width=\"256\">Transmission gates<\/td><td width=\"84\">34<\/td><\/tr><tr><td width=\"46\">113<\/td><td width=\"256\">CMOS Inverter<\/td><td width=\"84\">57<\/td><\/tr><tr><td width=\"46\">114<\/td><td width=\"256\">Designing using Cmos logic<\/td><td width=\"84\">53<\/td><\/tr><tr><td width=\"46\">115<\/td><td width=\"256\">VT FLAVOURS &amp; TIMING DELAYS<\/td><td width=\"84\">63<\/td><\/tr><tr><td width=\"46\">116<\/td><td width=\"256\">VT FLAVOURS &amp; TIMING DELAYS Part-2<\/td><td width=\"84\">7<\/td><\/tr><tr><td width=\"46\">117<\/td><td width=\"256\">Device Sizing<\/td><td width=\"84\">51<\/td><\/tr><tr><td width=\"46\">118<\/td><td width=\"256\">Device sizing continuation<\/td><td width=\"84\">41<\/td><\/tr><tr><td width=\"46\">119<\/td><td width=\"256\">Device sizing continuation Part2<\/td><td width=\"84\">29<\/td><\/tr><tr><td width=\"46\">120<\/td><td width=\"256\">Power Dissipation in CMOS<\/td><td width=\"84\">68<\/td><\/tr><tr><td width=\"46\">121<\/td><td width=\"256\">Continue power dissipation in CMOS<\/td><td width=\"84\">44<\/td><\/tr><tr><td width=\"46\">122<\/td><td width=\"256\">Short quiz<\/td><td width=\"84\">7<\/td><\/tr><tr><td width=\"46\">123<\/td><td width=\"256\">Layout<\/td><td width=\"84\">60<\/td><\/tr><tr><td width=\"46\">124<\/td><td width=\"256\">PD BASICS SES1<\/td><td width=\"84\">91<\/td><\/tr><tr><td width=\"46\">125<\/td><td width=\"256\">PD BASICS SES2<\/td><td width=\"84\">120<\/td><\/tr><tr><td width=\"46\">126<\/td><td width=\"256\">PD BASICS SES3<\/td><td width=\"84\">166<\/td><\/tr><tr><td width=\"46\">127<\/td><td width=\"256\">PD BASICS SES4<\/td><td width=\"84\">139<\/td><\/tr><tr><td width=\"46\">128<\/td><td width=\"256\">PD BASICS SES5<\/td><td width=\"84\">104<\/td><\/tr><tr><td width=\"46\">129<\/td><td width=\"256\">PD BASICS SES6<\/td><td width=\"84\">131<\/td><\/tr><tr><td width=\"46\">130<\/td><td width=\"256\">PD BASICS SES7<\/td><td width=\"84\">112<\/td><\/tr><tr><td width=\"46\">131<\/td><td width=\"256\">PD BASICS SES8<\/td><td width=\"84\">109<\/td><\/tr><\/tbody><\/table>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-curriculum-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-curriculum-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Curriculum<\/h5><p>\t\t\t\t\t\t\t<h3 style=\"margin-bottom:20px;display:block;width:100%;margin-top:10px\">Physical Design training <\/h3>\r\n\t\t\t\t\t\t<style>\r\n\t\t\t\t<style>\r\n#wpsm_accordion_9105 .wpsm_panel-heading{\r\n\tpadding:0px !important;\r\n}\r\n#wpsm_accordion_9105 .wpsm_panel-title {\r\n\tmargin:0px !important; \r\n\ttext-transform:none !important;\r\n\tline-height: 1 !important;\r\n}\r\n#wpsm_accordion_9105 .wpsm_panel-title a{\r\n\ttext-decoration:none;\r\n\toverflow:hidden;\r\n\tdisplay:block;\r\n\tpadding:0px;\r\n\tfont-size: 18px !important;\r\n\tfont-family: Open Sans !important;\r\n\tcolor:#000000 !important;\r\n\tborder-bottom:0px !important;\r\n}\r\n\r\n#wpsm_accordion_9105 .wpsm_panel-title a:focus {\r\noutline: 0px !important;\r\n}\r\n\r\n#wpsm_accordion_9105 .wpsm_panel-title a:hover, #wpsm_accordion_9105 .wpsm_panel-title a:focus {\r\n\tcolor:#000000 !important;\r\n}\r\n#wpsm_accordion_9105 .acc-a{\r\n\tcolor: #000000 !important;\r\n\tbackground-color:#e8e8e8 !important;\r\n\tborder-color: #ddd;\r\n}\r\n#wpsm_accordion_9105 .wpsm_panel-default > .wpsm_panel-heading{\r\n\tcolor: #000000 !important;\r\n\tbackground-color: #e8e8e8 !important;\r\n\tborder-color: #e8e8e8 !important;\r\n\tborder-top-left-radius: 0px;\r\n\tborder-top-right-radius: 0px;\r\n}\r\n#wpsm_accordion_9105 .wpsm_panel-default {\r\n\t\tborder:1px solid transparent !important;\r\n\t}\r\n#wpsm_accordion_9105 {\r\n\tmargin-bottom: 20px;\r\n\toverflow: hidden;\r\n\tfloat: none;\r\n\twidth: 100%;\r\n\tdisplay: block;\r\n}\r\n#wpsm_accordion_9105 .ac_title_class{\r\n\tdisplay: block;\r\n\tpadding-top: 12px;\r\n\tpadding-bottom: 12px;\r\n\tpadding-left: 15px;\r\n\tpadding-right: 15px;\r\n}\r\n#wpsm_accordion_9105  .wpsm_panel {\r\n\toverflow:hidden;\r\n\t-webkit-box-shadow: 0 0px 0px rgba(0, 0, 0, .05);\r\n\tbox-shadow: 0 0px 0px rgba(0, 0, 0, .05);\r\n\t\tborder-radius: 4px;\r\n\t}\r\n#wpsm_accordion_9105  .wpsm_panel + .wpsm_panel {\r\n\t\tmargin-top: 5px;\r\n\t}\r\n#wpsm_accordion_9105  .wpsm_panel-body{\r\n\tbackground-color:#ffffff !important;\r\n\tcolor:#000000 !important;\r\n\tborder-top-color: #e8e8e8 !important;\r\n\tfont-size:16px !important;\r\n\tfont-family: Open Sans !important;\r\n\toverflow: hidden;\r\n\t\tborder: 2px solid #e8e8e8 !important;\r\n\t}\r\n\r\n#wpsm_accordion_9105 .ac_open_cl_icon{\r\n\tbackground-color:#e8e8e8 !important;\r\n\tcolor: #000000 !important;\r\n\tfloat:right !important;\r\n\tpadding-top: 12px !important;\r\n\tpadding-bottom: 12px !important;\r\n\tline-height: 1.0 !important;\r\n\tpadding-left: 15px !important;\r\n\tpadding-right: 15px !important;\r\n\tdisplay: inline-block !important;\r\n}\r\n\r\n\t\t\t\r\n\t\t\t<\/style>\t\r\n\t\t\t<\/style>\r\n\t\t\t<div class=\"wpsm_panel-group\" id=\"wpsm_accordion_9105\" >\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse1\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-minus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tEDA Tools Used in Physical Design Flow\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse1\" class=\"wpsm_panel-collapse collapse in\"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<table border=\"1\" cellpadding=\"8\" cellspacing=\"0\" width=\"100%\">\r\n<tr>\r\n<th>PD Flow Stage<\/th>\r\n<th>Synopsys Tool<\/th>\r\n<th>Cadence Tool<\/th>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>RTL to Gate Synthesis<\/td>\r\n<td>Design Compiler (DC)<\/td>\r\n<td>Genus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Floorplanning &amp; Placement<\/td>\r\n<td>IC Compiler II (ICC2)<\/td>\r\n<td>Innovus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Power Planning<\/td>\r\n<td>ICC2 \/ PrimePower<\/td>\r\n<td>Innovus \/ Voltus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Clock Tree Synthesis (CTS)<\/td>\r\n<td>ICC2<\/td>\r\n<td>Innovus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Routing (Global + Detailed)<\/td>\r\n<td>ICC2<\/td>\r\n<td>Innovus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Parasitic Extraction (PEX)<\/td>\r\n<td>StarRC<\/td>\r\n<td>Quantus QRC<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Timing Analysis (STA)<\/td>\r\n<td>PrimeTime<\/td>\r\n<td>Tempus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Signal Integrity (SI)<\/td>\r\n<td>PrimeTime SI \/ StarRC<\/td>\r\n<td>Tempus SI \/ Quantus QRC<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Power Integrity (IR\/EM)<\/td>\r\n<td>RedHawk-SC (via ANSYS)<\/td>\r\n<td>Voltus<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Formal Equivalence Checking<\/td>\r\n<td>Formality<\/td>\r\n<td>Conformal<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>Physical Verification (DRC\/LVS\/ERC)<\/td>\r\n<td>IC Validator (ICV)<\/td>\r\n<td>Pegasus \/ PVS<\/td>\r\n<\/tr>\r\n\r\n<tr>\r\n<td>GDSII Generation<\/td>\r\n<td>ICC2<\/td>\r\n<td>Innovus<\/td>\r\n<\/tr>\r\n\r\n<\/table>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse2\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tVLSI Design flow\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse2\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<h3>Specification &amp; Design Flow<\/h3>\r\n\r\n<ul>\r\n  <li>Specification<\/li>\r\n  <li>RTL Coding &amp; Lint Checks<\/li>\r\n  <li>RTL Integration<\/li>\r\n  <li>Connectivity Checks<\/li>\r\n  <li>Functional Verification<\/li>\r\n  <li>Synthesis &amp; STA<\/li>\r\n  <li>Gate Level Simulations<\/li>\r\n  <li>Power Aware Simulations<\/li>\r\n  <li>Placement and Routing<\/li>\r\n  <li>DFT<\/li>\r\n  <li>Custom Layout<\/li>\r\n  <li>Post Silicon Validation<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse3\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tSemiconductor device fundamentals\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse3\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<h3>Transistors in Hardware Design<\/h3>\r\n<ul>\r\n  <li>Significance of transistors in hardware design<\/li>\r\n  <li>Logic gate implementation using BJT, CMOS<\/li>\r\n  <li>MOSFET functionality<\/li>\r\n<\/ul>\r\n\r\n<h3>Semiconductors<\/h3>\r\n<ul>\r\n  <li>What makes Semiconductor special element?<\/li>\r\n  <li>Classification of solids into three types<\/li>\r\n  <li>Conductor, Insulator, Semiconductor<\/li>\r\n  <li>Energy bands in Solids<\/li>\r\n  <li>Types of Semiconductors<\/li>\r\n  <li>Intrinsic Semiconductors<\/li>\r\n  <li>Extrinsic Semiconductors<\/li>\r\n  <li>Types of Extrinsic Semiconductors<\/li>\r\n  <li>N-type Extrinsic Semiconductor<\/li>\r\n  <li>P-type Extrinsic Semiconductor<\/li>\r\n  <li>Si, Ge \u2013 comparison<\/li>\r\n  <li>Types of current in Semiconductors \u2013 Drift, Diffusion<\/li>\r\n  <li>Ion<\/li>\r\n<\/ul>\r\n\r\n<h3>PN Junction Diode<\/h3>\r\n<ul>\r\n  <li>PN Junction \u2013 forward, reverse bias<\/li>\r\n  <li>V-I Characteristics of PN Junction Diode<\/li>\r\n  <li>Different types of Diode<\/li>\r\n  <li>Applications of Diode<\/li>\r\n<\/ul>\r\n\r\n<h3>BJT<\/h3>\r\n<ul>\r\n  <li>BJT<\/li>\r\n  <li>BJT working principle<\/li>\r\n  <li>How BJT can be used for large scale manufacturing<\/li>\r\n  <li>BJT fabrication steps<\/li>\r\n  <li>Types of BJT<\/li>\r\n  <li>Why BJT is not used in lower technology nodes<\/li>\r\n  <li>Issues with BJT<\/li>\r\n  <li>Advantages of BJT<\/li>\r\n  <li>NAND gate using BJT<\/li>\r\n<\/ul>\r\n\r\n<h3>Field Effect Transistor (FET)<\/h3>\r\n<ul>\r\n  <li>What is Field Effect Transistor?<\/li>\r\n  <li>Types of FET<\/li>\r\n  <li>NMOS<\/li>\r\n  <li>PMOS<\/li>\r\n  <li>CMOS<\/li>\r\n  <li>Fin<\/li>\r\n<\/ul>\r\n\r\n<h3>NMOS<\/h3>\r\n<ul>\r\n  <li>What is NMOS?<\/li>\r\n  <li>NMOS working principle<\/li>\r\n  <li>Different voltages, currents, their equations<\/li>\r\n  <li>NMOS circuit representation<\/li>\r\n  <li>How NMOS works like a switch<\/li>\r\n  <li>How NMOS can be used for large scale manufacturing<\/li>\r\n  <li>NMOS fabrication steps<\/li>\r\n  <li>Types of NMOS<\/li>\r\n  <li>Why CMOS is used instead of NMOS<\/li>\r\n  <li>Issues with NMOS<\/li>\r\n  <li>Advantages of NMOS<\/li>\r\n  <li>NAND gate using NMOS<\/li>\r\n<\/ul>\r\n\r\n<h3>CMOS<\/h3>\r\n<ul>\r\n  <li>What is CMOS?<\/li>\r\n  <li>CMOS working principle<\/li>\r\n  <li>Different voltages, currents, their equations<\/li>\r\n  <li>CMOS circuit representation<\/li>\r\n  <li>How CMOS works like a switch<\/li>\r\n  <li>How CMOS can be used for large scale manufacturing<\/li>\r\n  <li>CMOS fabrication steps<\/li>\r\n  <li>Types of CMOS<\/li>\r\n  <li>Issues with CMOS<\/li>\r\n  <li>Advantages of CMOS<\/li>\r\n  <li>NAND gate using CMOS<\/li>\r\n  <li>CMOS second order effects<\/li>\r\n<\/ul>\r\n\r\n<h3>FinFET<\/h3>\r\n<ul>\r\n  <li>What is FinFET?<\/li>\r\n  <li>FinFET working principle<\/li>\r\n  <li>Different voltages, currents, their equations<\/li>\r\n  <li>Circuit representation<\/li>\r\n  <li>How FinFET works like a switch<\/li>\r\n  <li>How FinFET can be used for large scale manufacturing<\/li>\r\n  <li>FinFET fabrication steps<\/li>\r\n  <li>Types of FinFET<\/li>\r\n  <li>Issues with FinFET<\/li>\r\n  <li>Advantages of FinFET<\/li>\r\n  <li>NAND gate using FinFET<\/li>\r\n  <li>FinFET second order effects<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse4\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tIC fabrication\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse4\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Layers of CMOS<\/li>\r\n  <li>Depositing Oxide Layer<\/li>\r\n  <li>Photolithography<\/li>\r\n  <li>Masking<\/li>\r\n  <li>Etching Layers<\/li>\r\n  <li>Formation of N-Well<\/li>\r\n  <li>Self-Aligned Gate Fabrication Process<\/li>\r\n  <li>Diffusion to Create N+ and P+ Regions<\/li>\r\n  <li>Metallization<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse5\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tAdvanced Digital Design\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse5\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<h3>Combinational Logic<\/h3>\r\n<ul>\r\n  <li>Number Systems<\/li>\r\n  <li>Radix Conversions<\/li>\r\n  <li>K-Maps, Min-terms, Max Terms<\/li>\r\n  <li>Logic Gates<\/li>\r\n  <li>Realization of Logic Gates using MUXs and Universal Gates<\/li>\r\n  <li>Complements (1\u2019s \/ 2\u2019s \/ 9\u2019s \/ 10\u2019s Complement)<\/li>\r\n  <li>Arithmetic Operations using Complements<\/li>\r\n  <li>Boolean Expression Minimization, DeMorgan Theorems<\/li>\r\n  <li>POS and SOP<\/li>\r\n  <li>Conversion and Realization<\/li>\r\n\r\n  <li>Adders\r\n    <ul>\r\n      <li>Half Adder<\/li>\r\n      <li>Full Adder<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n\r\n  <li>Subtractors\r\n    <ul>\r\n      <li>Half Subtractor<\/li>\r\n      <li>Full Subtractor<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n\r\n  <li>Multiplexers<\/li>\r\n  <li>Realizing Bigger MUXs using Smaller MUXs<\/li>\r\n  <li>Implementing Adders and Subtractors using Multiplexers<\/li>\r\n  <li>Decoders and Encoders<\/li>\r\n  <li>Implementing Decoders and Encoders using MUX and DEMUX<\/li>\r\n  <li>Bigger Decoder\/Encoder using Smaller Decoder\/Encoder<\/li>\r\n  <li>Comparators<\/li>\r\n  <li>Implementing Multi-bit Comparators using 1-bit Comparator<\/li>\r\n<\/ul>\r\n\r\n\r\n<h3>Sequential Logic<\/h3>\r\n<ul>\r\n  <li>Latch, Flip-Flop<\/li>\r\n  <li>Latch, Flip-Flop using Gates or MUXs<\/li>\r\n  <li>Different Types of Flip-Flops<\/li>\r\n  <li>Flip-Flop Truth Table<\/li>\r\n  <li>Excitation Tables<\/li>\r\n  <li>Realization of Flip-Flops using Other Flip-Flops<\/li>\r\n\r\n  <li>Applications of Flip-Flops and Latches\r\n    <ul>\r\n      <li>Counters<\/li>\r\n      <li>Shift Registers<\/li>\r\n      <li>Synchronizers for Clock Domain Crossing<\/li>\r\n      <li>FSMs<\/li>\r\n      <li>Mealy and Moore FSM<\/li>\r\n      <li>Different Encoding Styles<\/li>\r\n      <li>Frequency Dividers<\/li>\r\n      <li>Frequency Multiplication<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n\r\n  <li>Static Timing Analysis (STA)\r\n    <ul>\r\n      <li>Setup Time, Hold Time, Timing Closure<\/li>\r\n      <li>Fixing Setup and Hold Time Violations<\/li>\r\n      <li>Launch Flop and Capture Flop<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse6\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPD flow keywords and VLSI Technology concepts\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse6\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Introduction to majorly used keywords on PD flow<\/li>\r\n\r\n  <li>VLSI Technology concepts\r\n    <ul>\r\n      <li>Resistance, Capacitance, Inductance<\/li>\r\n      <li>Parasitic capacitance<\/li>\r\n      <li>L-C-R circuit analysis<\/li>\r\n      <li>RC circuit significance with circuit delay<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n\r\n  <li>Clock distribution concepts, skew<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse7\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tLinux commands \u2013 hands on training\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse7\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Installing Linux platform in Windows<\/li>\r\n  <li>Linux Basics<\/li>\r\n  <li>Linux versus Windows<\/li>\r\n  <li>Linux Terminal<\/li>\r\n  <li>File and Directory Management<\/li>\r\n  <li>Changing File Permissions<\/li>\r\n  <li>Absolute Path and Relative Path<\/li>\r\n  <li>Working with Directories<\/li>\r\n  <li>GVIM \u2013 Major Keyboard Shortcuts<\/li>\r\n  <li>Text Display Commands<\/li>\r\n  <li>Root Configuration Files<\/li>\r\n  <li>Environment Variables<\/li>\r\n\r\n  <li>Text Processing Commands\r\n    <ul>\r\n      <li>grep, fgrep<\/li>\r\n      <li>xargs<\/li>\r\n      <li>SED<\/li>\r\n      <li>AWK<\/li>\r\n      <li>Pipes and Filters<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n\r\n  <li>Connecting to Server<\/li>\r\n  <li>Process Management<\/li>\r\n  <li>LSF<\/li>\r\n  <li>Ping<\/li>\r\n  <li>FTP<\/li>\r\n  <li>CTAGs<\/li>\r\n  <li>File Compress and Extract<\/li>\r\n  <li>Soft Links<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse8\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tTCL scripting\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse8\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Overview<\/li>\r\n  <li>Env Setup<\/li>\r\n  <li>Special Variables<\/li>\r\n  <li>Data Types<\/li>\r\n  <li>Variables<\/li>\r\n  <li>Operators<\/li>\r\n  <li>Decisions<\/li>\r\n  <li>Loops<\/li>\r\n  <li>Arrays, Strings, Lists, Dictionary<\/li>\r\n  <li>History and Redoing of Commands<\/li>\r\n  <li>String Pattern Matching Commands<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse9\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPhysical design main course syllabus (Duration: 4 months) Synthesis\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse9\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Basics of Synthesis<\/li>\r\n  <li>High Level Synthesis Flow<\/li>\r\n  <li>Reading of Verilog RTL File<\/li>\r\n  <li>Target and Link Libraries<\/li>\r\n  <li>Resolving References with Link Libraries<\/li>\r\n  <li>Reading Hierarchical Designs<\/li>\r\n  <li>Reading DDC Design<\/li>\r\n  <li>Analyze &amp; Elaborate Commands<\/li>\r\n  <li>Constraining and Compiling RTL<\/li>\r\n  <li>Post Synthesis Output Data<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse10\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tTiming Constraints\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse10\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Constraining Register to Register Paths<\/li>\r\n  <li>Constraining Input Paths<\/li>\r\n  <li>Constraining Output Paths<\/li>\r\n  <li>Virtual Clock<\/li>\r\n  <li>Load Budgeting<\/li>\r\n  <li>Default Path Groups<\/li>\r\n  <li>Creating User-defined Path Groups<\/li>\r\n  <li>Prioritizing Path Groups<\/li>\r\n  <li>Timing Reports<\/li>\r\n  <li>Analyzing Timing Reports<\/li>\r\n  <li>Defining a Clock with Additional Options<\/li>\r\n  <li>Input Delay with Additional Options<\/li>\r\n  <li>Output Delay with Additional Options<\/li>\r\n  <li>Pre-CTS versus Post-CTS Clock Latencies<\/li>\r\n  <li>Independent IO Latencies<\/li>\r\n  <li>Output Delay with Network Latency<\/li>\r\n  <li>Output Delay with Source Latency<\/li>\r\n  <li>Different IO versus Internal Latencies<\/li>\r\n  <li>IO Clock Latencies<\/li>\r\n  <li>Handling Different IO vs Internal Latencies<\/li>\r\n  <li>Virtual External Clock Latencies<\/li>\r\n  <li>Included External Clock Latencies<\/li>\r\n  <li>Multiple Synchronous Clocks<\/li>\r\n  <li>Multiple Clocks Input Delay<\/li>\r\n  <li>Maximum Internal Input Delay<\/li>\r\n  <li>Multiple Clock Output Delay<\/li>\r\n  <li>Maximum Internal Output Delay<\/li>\r\n  <li>Inter Clock Uncertainty<\/li>\r\n  <li>Generated Clocks<\/li>\r\n  <li>Mutual Exclusive Synchronous Clocks<\/li>\r\n  <li>Logically Exclusive Clocks<\/li>\r\n  <li>Multiple Clocks per Register<\/li>\r\n  <li>Cross Talk Analysis<\/li>\r\n  <li>Asynchronous Clocks<\/li>\r\n  <li>Multi Cycle Paths and Constraints<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse11\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tUPF\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse11\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>High Level Multi-Voltage Design Concepts<\/li>\r\n  <li>Supplies and Power Domains<\/li>\r\n  <li>Power Ports and Nets<\/li>\r\n  <li>Level Shifters<\/li>\r\n  <li>Power States and PS Table<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse12\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tNDM Libraries\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse12\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>IC Compiler II Library Manager<\/li>\r\n  <li>ICC Compiler II NDM Cell Library<\/li>\r\n  <li>Cell Library Characteristics<\/li>\r\n  <li>Library Manager Flow<\/li>\r\n  <li>Tech Only NDM Library<\/li>\r\n  <li>Technology-Only Library Flow<\/li>\r\n  <li>Technology File<\/li>\r\n  <li>Read TLU+ Files<\/li>\r\n  <li>Tech Library Preparation<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse13\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tInitial Design Setup\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse13\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Top Level, Sub-System Level and Block Level Design Setup<\/li>\r\n  <li>Set Up Initial Design Implementation<\/li>\r\n  <li>Loading Netlist from Synthesis<\/li>\r\n  <li>Setting Path to .lib Files, LEFs, DEFs (if needed), Technology Files, SDC Files<\/li>\r\n  <li>Flow Setup and Design Setup<\/li>\r\n  <li>Loop-back to Synthesis for Correlation Issues Correction<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse14\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tFloor Planning\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse14\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Initial Floorplanning Settings<\/li>\r\n  <li>Define Pad Instances (Physical Cells)<\/li>\r\n  <li>Pad Instance Coordinates<\/li>\r\n  <li>Start Floorplanning<\/li>\r\n  <li>Core Die Size Setting<\/li>\r\n  <li>Floorplanning of Pad Instances<\/li>\r\n  <li>Pad Filler Insertion<\/li>\r\n  <li>Define Pad Ring Power Grid<\/li>\r\n  <li>Macro Instance Constraints<\/li>\r\n  <li>Macro Instance Array Creation<\/li>\r\n  <li>Macro Instance Orientation<\/li>\r\n  <li>Anchor-Based and Relative Placement of Macro Instances<\/li>\r\n  <li>Macro Instance Channel Settings<\/li>\r\n  <li>Macro Instance Placement \u2013 Manual<\/li>\r\n  <li>Congestion Probability Around Macro Instances<\/li>\r\n  <li>Defining Placement Blockages<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse15\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPlacement\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse15\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Running Placement<\/li>\r\n  <li>Defining Placement Strategies<\/li>\r\n  <li>In-Place Optimization (IPO)<\/li>\r\n  <li>Hierarchical Placement<\/li>\r\n  <li>Relative Placement<\/li>\r\n  <li>Congestion Analysis and Reduction<\/li>\r\n  <li>Macro Placement Changes to Reduce Congestion<\/li>\r\n  <li>Standard Cell Placement Constraints<\/li>\r\n  <li>Halo Creation for Instances<\/li>\r\n  <li>Congestion Analysis with Standard Cell Placement<\/li>\r\n  <li>Local Congestion Reduction<\/li>\r\n  <li>Density Screen and Placement Blockage for Standard Cells<\/li>\r\n  <li>Congestion Aware Placement<\/li>\r\n  <li>Re-Check Macro Placement for Better Congestion Relief<\/li>\r\n  <li>Create Balanced Buffer Trees for High Fanout Net<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse16\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPower Planning\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse16\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Defining Power Structure<\/li>\r\n  <li>Logical Power\/Ground Connections<\/li>\r\n  <li>Setting Power Network Constraints<\/li>\r\n  <li>Create and Analyze Power Structure<\/li>\r\n  <li>Change Power Constraints and Re-Create to Meet IR Requirements<\/li>\r\n  <li>Power\/Ground Pin Connection and Create Power Rails<\/li>\r\n  <li>Power Network Checks for IR and Resistance<\/li>\r\n  <li>Placement Blockage for Power Network<\/li>\r\n  <li>Incremental Placement<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse17\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tScan Chain RE-Ordering and RE-Partitioning\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse17\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Re-Order Scan Connectivity within Chain<\/li>\r\n  <li>Re-Partition Scan Connectivity across Chains<\/li>\r\n  <li>SCANDEF File-Based Scan Chain Re-Ordering<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse18\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tGlobal Routing\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse18\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Congestion Checks for Overflow Again<\/li>\r\n  <li>RC Extraction for Net Parasitics<\/li>\r\n  <li>Check Timing for Max Analysis<\/li>\r\n  <li>Run Timing\/Congestion Aware Placement<\/li>\r\n  <li>Logic Re-Structuring for Placement and Timing<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse19\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tClock Tree Synthesis\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse19\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Check Pre-CTS Timing Based on Global Routing and Detailed Placement<\/li>\r\n  <li>Setting Clock Constraints such as Target Skew and Target Insertion Delay<\/li>\r\n  <li>Clock Root Attributes as Stop, Float and Exclude Pins<\/li>\r\n  <li>Building for Generated and Gated Clocks<\/li>\r\n  <li>Don\u2019t Touch Attribute on Existing Clock Tree Structure<\/li>\r\n  <li>Defining Clock Buffers and Inverters<\/li>\r\n  <li>Set Clock Tree Timing DRCs<\/li>\r\n  <li>Non-Default Clock Routing Rules Setting<\/li>\r\n  <li>Perform Clock Tree Synthesis and Clock Tree Optimization<\/li>\r\n  <li>Reduce Hold Violations in Data Paths and Scan Paths<\/li>\r\n  <li>Clock Tree Building\/Optimization for Multiple Modes and Multiple PVT Corners<\/li>\r\n  <li>Synchronous Clock Balancing<\/li>\r\n  <li>Cross-Clock Delay Balancing<\/li>\r\n  <li>Logical Hierarchy Aware CTS<\/li>\r\n  <li>Max and Min Analysis and Subsequent Optimization<\/li>\r\n  <li>Fixing Violations<\/li>\r\n  <li>CTS Optimization Across Other Modes and PVT Corners (MMMC)<\/li>\r\n  <li>Skew and Insertion Delay Checks<\/li>\r\n  <li>Checking Crosstalk on Clock Network<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse20\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tDetailed Routing\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse20\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Pre-Route Check Points<\/li>\r\n  <li>Routing Fundamentals<\/li>\r\n  <li>Global Route<\/li>\r\n  <li>Detailed Routing<\/li>\r\n  <li>Track Assignment and Route<\/li>\r\n  <li>Refining Detailed Route<\/li>\r\n  <li>Over-the-Macro Routing<\/li>\r\n  <li>Non-Preferred Routing Direction<\/li>\r\n  <li>Clock Net Routing<\/li>\r\n  <li>Initial Data Path Routing<\/li>\r\n  <li>Redundant VIA Insertion Setting<\/li>\r\n  <li>Post Detailed Route Optimization<\/li>\r\n  <li>Fixing DRC Violations<\/li>\r\n  <li>Post Detailed Route Delay Calculation Algorithms<\/li>\r\n  <li>Crosstalk Delay and Noise Analysis and Fix<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse21\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPower Analysis (Static and Dynamic)\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse21\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Check Leakage Power Dissipation<\/li>\r\n  <li>VT Cell Swap for Power and Timing Trade-Off<\/li>\r\n  <li>Analyzing Dynamic Power Dissipation Based on GAF, SAIF, VCD<\/li>\r\n  <li>Reduce Dynamic Power<\/li>\r\n  <li>Meet Total Power Target<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse22\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tEngineering Change Order Flow (ECO)\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse22\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Functional ECO<\/li>\r\n  <li>Timing ECO<\/li>\r\n  <li>Metal-Only ECO Using Spare Cells for Base Frozen Designs<\/li>\r\n<\/ul>\r\n\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse23\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tMultiple Industry standard Projects\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse23\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>\r\n    Projects covering detailed flow from Input Files, Floorplan, Power Planning, Placement, CTS, Routing, SPEF Extraction, STA, and Physical Verification\r\n    <ul>\r\n      <li>One Project Completely Guided by the Trainer<\/li>\r\n      <li>Other Project Done by Student with Trainer Guidance<\/li>\r\n    <\/ul>\r\n  <\/li>\r\n  <li>Project Based on Multi-Voltage Domain<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9105 \" href=\"javascript:void(0)\" data-target=\"#ac_9105_collapse24\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tDesign For Manufacturability\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9105_collapse24\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n  <li>Antenna Rules and Fixes<\/li>\r\n  <li>Critical Area Analysis<\/li>\r\n  <li>Wire Spreading and Widening<\/li>\r\n  <li>Setting Minimum Metal Jog Length<\/li>\r\n  <li>Filler Cell Insertion<\/li>\r\n  <li>Metal Fill<\/li>\r\n  <li>Timing Checks After Metal Fill<\/li>\r\n  <li>Parasitic Extraction for Signoff Timing Analysis<\/li>\r\n  <li>Export Netlist<\/li>\r\n  <li>Export GDSII<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\r\n<script type=\"text\/javascript\">\r\n\t\r\n\t\tfunction do_resize(){\r\n\r\n\t\t\tvar width=jQuery( '.wpsm_panel .wpsm_panel-body iframe' ).width();\r\n\t\t\tvar height=jQuery( '.wpsm_panel .wpsm_panel-body iframe' ).height();\r\n\r\n\t\t\tvar toggleSize = true;\r\n\t\t\tjQuery('iframe').animate({\r\n\t\t\t    width: toggleSize ? width : 640,\r\n\t\t\t    height: toggleSize ? height : 360\r\n\t\t\t  }, 250);\r\n\r\n\t\t\t  toggleSize = !toggleSize;\r\n\t\t}\r\n\t\t\r\n<\/script>\t<\/p>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"benefits-of-elearning-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"benefits-of-elearning-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Benefits of eLearning?<\/h5><div class=\"course-list\"><ul><li>Access to the Instructor - Ask questions to the Instructor who taught the course<\/li><li>Available 24\/7 - VLSIGuru eLearning courses are available when and where you need them<\/li><li>Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready<\/li><\/ul><\/div>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-instructor-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-instructor-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Course Instructor<\/h5><div class=\"course-list\"><ul><li>Sreenivas Reddy \u2014 Founder, VLSIGuru<\/li><\/ul><\/div>\t\t\t\t                            <\/div>\n\t\t                    <\/div>\n        <\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-3280dea\" data-id=\"3280dea\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-d661710 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"d661710\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-inner-column elementor-element elementor-element-dcb7290\" data-id=\"dcb7290\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-90aa368 elementor-widget elementor-widget-video\" data-id=\"90aa368\" data-element_type=\"widget\" data-settings=\"{&quot;youtube_url&quot;:&quot;https:\\\/\\\/youtu.be\\\/xvmFO85CooQ&quot;,&quot;show_image_overlay&quot;:&quot;yes&quot;,&quot;image_overlay&quot;:{&quot;url&quot;:&quot;https:\\\/\\\/inskill.in\\\/training\\\/wp-content\\\/uploads\\\/2023\\\/03\\\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg&quot;,&quot;id&quot;:485,&quot;size&quot;:&quot;&quot;,&quot;alt&quot;:&quot;&quot;,&quot;source&quot;:&quot;library&quot;},&quot;lightbox&quot;:&quot;yes&quot;,&quot;video_type&quot;:&quot;youtube&quot;,&quot;controls&quot;:&quot;yes&quot;}\" data-widget_type=\"video.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-video .elementor-widget-container{overflow:hidden;transform:translateZ(0)}.elementor-widget-video .elementor-wrapper iframe,.elementor-widget-video .elementor-wrapper video{height:100%;width:100%;border:none;background-color:#000}.elementor-widget-video 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data-elementor-lightbox=\"{&quot;type&quot;:&quot;video&quot;,&quot;videoType&quot;:&quot;youtube&quot;,&quot;url&quot;:&quot;https:\\\/\\\/www.youtube.com\\\/embed\\\/xvmFO85CooQ?feature=oembed&amp;start&amp;end&amp;wmode=opaque&amp;loop=0&amp;controls=1&amp;mute=0&amp;rel=0&amp;modestbranding=0&quot;,&quot;modalOptions&quot;:{&quot;id&quot;:&quot;elementor-lightbox-90aa368&quot;,&quot;entranceAnimation&quot;:&quot;&quot;,&quot;entranceAnimation_tablet&quot;:&quot;&quot;,&quot;entranceAnimation_mobile&quot;:&quot;&quot;,&quot;videoAspectRatio&quot;:&quot;169&quot;}}\" data-e-action-hash=\"#elementor-action%3Aaction%3Dlightbox%26settings%3DeyJ0eXBlIjoidmlkZW8iLCJ2aWRlb1R5cGUiOiJ5b3V0dWJlIiwidXJsIjoiaHR0cHM6XC9cL3d3dy55b3V0dWJlLmNvbVwvZW1iZWRcL3h2bUZPODVDb29RP2ZlYXR1cmU9b2VtYmVkJnN0YXJ0JmVuZCZ3bW9kZT1vcGFxdWUmbG9vcD0wJmNvbnRyb2xzPTEmbXV0ZT0wJnJlbD0wJm1vZGVzdGJyYW5kaW5nPTAiLCJtb2RhbE9wdGlvbnMiOnsiaWQiOiJlbGVtZW50b3ItbGlnaHRib3gtOTBhYTM2OCIsImVudHJhbmNlQW5pbWF0aW9uIjoiIiwiZW50cmFuY2VBbmltYXRpb25fdGFibGV0IjoiIiwiZW50cmFuY2VBbmltYXRpb25fbW9iaWxlIjoiIiwidmlkZW9Bc3BlY3RSYXRpbyI6IjE2OSJ9fQ%3D%3D\">\n\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"427\" height=\"360\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg\" class=\"attachment-full size-full wp-image-485\" alt=\"\" srcset=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg 427w, https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1-300x253.jpg 300w\" sizes=\"auto, (max-width: 427px) 100vw, 427px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5b12bfa elementor-widget elementor-widget-wpr-elementor-template\" data-id=\"5b12bfa\" data-element_type=\"widget\" data-widget_type=\"wpr-elementor-template.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div data-elementor-type=\"section\" data-elementor-id=\"511\" class=\"elementor elementor-511\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e1113af elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e1113af\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-0269498\" data-id=\"0269498\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-8885478 elementor-align-center elementor-widget__width-initial opopii elementor-widget elementor-widget-button\" data-id=\"8885478\" data-element_type=\"widget\" data-widget_type=\"button.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-button-wrapper\">\n\t\t\t<a href=\"https:\/\/inskill.in\/online\/course_enrol.php\" class=\"elementor-button-link elementor-button elementor-size-lg\" role=\"button\">\n\t\t\t\t\t\t<span class=\"elementor-button-content-wrapper\">\n\t\t\t\t\t\t<span class=\"elementor-button-text\">ENROLL NOW<\/span>\n\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t<span class=\"wpr-template-edit-btn\" data-permalink=\"https:\/\/inskill.in\/training\/?elementor_library=button\">Edit Template<\/span>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-75b71e7 elementor-widget elementor-widget-wpr-elementor-template\" data-id=\"75b71e7\" data-element_type=\"widget\" data-widget_type=\"wpr-elementor-template.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div data-elementor-type=\"section\" data-elementor-id=\"500\" class=\"elementor elementor-500\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-bb3a73c elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"bb3a73c\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-inner-column elementor-element elementor-element-14950a6\" data-id=\"14950a6\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-186e1a84 elementor-widget elementor-widget-heading\" data-id=\"186e1a84\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Course Highlights<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-1246868c elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"1246868c\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-user-secret\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">1-1 mentor support<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-user-injured\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Mentor guidance support for assignments<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-compass\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Multiple mock interviews<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-clipboard\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Dedicated live support sessions over weekends<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t<span class=\"wpr-template-edit-btn\" data-permalink=\"https:\/\/inskill.in\/training\/?elementor_library=course_highlights\">Edit Template<\/span>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-91fa43f elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"91fa43f\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;slideshow&quot;,&quot;background_slideshow_gallery&quot;:[{&quot;id&quot;:438,&quot;url&quot;:&quot;https:\\\/\\\/inskill.in\\\/training\\\/wp-content\\\/uploads\\\/2023\\\/02\\\/vlsi-img.jpg&quot;}],&quot;background_slideshow_loop&quot;:&quot;yes&quot;,&quot;background_slideshow_slide_duration&quot;:5000,&quot;background_slideshow_slide_transition&quot;:&quot;fade&quot;,&quot;background_slideshow_transition_duration&quot;:500}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-c8dece7\" data-id=\"c8dece7\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e8d88d3 elementor-widget elementor-widget-heading\" data-id=\"e8d88d3\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<p class=\"elementor-heading-title elementor-size-default\">TESTIMONIALS<\/p>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-948db1c elementor-widget elementor-widget-heading\" data-id=\"948db1c\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">What Our Students Says About Inskill\n<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8c7308a wpr-testimonial-slider-columns-2 wpr-testimonial-slider-columns--tablet2 wpr-testimonial-slider-columns--mobile1 wpr-testimonial-rating-style_2 wpr-testimonial-triangle-yes wpr-testimonial-meta-position-bottom wpr-testimonial-meta-align-center wpr-testimonial-image-position-center elementor-widget elementor-widget-wpr-testimonial\" data-id=\"8c7308a\" data-element_type=\"widget\" data-settings=\"{&quot;testimonial_amount&quot;:2,&quot;testimonial_amount_tablet&quot;:2,&quot;testimonial_amount_mobile&quot;:1,&quot;testimonial_slides_to_scroll&quot;:2,&quot;testimonial_loop&quot;:&quot;yes&quot;}\" data-widget_type=\"wpr-testimonial.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"wpr-testimonial-carousel-wrap\">\r\n\t\t\t\r\n\t\t\t<div class=\"wpr-testimonial-carousel\" dir=\"ltr\" data-slick=\"{&quot;rtl&quot;:false,&quot;infinite&quot;:true,&quot;speed&quot;:700,&quot;arrows&quot;:true,&quot;dots&quot;:true,&quot;autoplay&quot;:false,&quot;autoplaySpeed&quot;:0,&quot;pauseOnHover&quot;:&quot;&quot;,&quot;prevArrow&quot;:&quot;#wpr-testimonial-prev-8c7308a&quot;,&quot;nextArrow&quot;:&quot;#wpr-testimonial-next-8c7308a&quot;,&quot;sliderSlidesToScroll&quot;:2}\" data-slide-effect=\"slide\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-c1659f3 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img1.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">ONKAR JOSHI <\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-6\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.<br \/>The admins are very much co-operative and understandable and help you throughout the course.<br \/>The concepts taught are in a very simplified manner and every lecture is recorded.<br \/>Very much satisfied will recommend to any VLSI enthusiast<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">7 Days Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-ee54814 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img2.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Uday G R<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-8\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>VLSIGURU training institute is one of the best training institute for VLSI domain.<br \/>They offer best courses for a very low and affordable prices.<br \/>I took e-learning courses, the course content and materials are well planned according to the industry requirements.<br \/>Their lectures are very detailed and cover all the concepts.<br \/>The projects and assignments they give are helpful in cracking a job.<br \/>The admin teams is very supportive all the time. I would definitely recommend to others<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">10.04.2018<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-433c82d elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img4.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Vinutha M B<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-7\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I have taken training at VLSIGURU for Design and functional verification course through online, <br \/>where i got more practical knowledge then usual syllabuses.<br \/>I was very much satisfied learning at this training institute. <br \/>Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience <br \/>which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period. <br \/>every sessions recorded and can be accessed through their website when required. <br \/>The institute also provided hands-on experience with the required tools and provide online access as well. <br \/>This institute has highly well experienced real time working professionals as trainers. <br \/>thanks to VLSIGURU institute.<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">5 Month Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-e67c709 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img5.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Beulah Grace<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-6\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I have taken training at VLSIGURU for Design and Verification course through online. <br \/>They have very experienced faculty with industrial knowledge. <br \/>The trainers explained every concept from the very basic to core concepts with good explanation. <br \/>Every doubt has been clarified with patience and in detail. <br \/>Every session os recorded and can be accessed through their website when required. <br \/>The institute also provided hands-on experience with the required tools and provided online access as well. <br \/>VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts. <br \/>Interview preparation sessions has also been conducted along with mock interviews and training sessions.<br \/>It is the best institute to gain knowledge in core domain with affordable prices. <br \/>I Thank VLSIGURU for helping me to gain knowledge in the core domain.<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">6 Month Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t<div class=\"wpr-testimonial-controls\">\r\n\t\t\t\t<div class=\"wpr-testimonial-dots\"><\/div>\r\n\t\t\t<\/div>\r\n\r\n\t\t\t<div class=\"wpr-testimonial-arrow-container\">\r\n\t\t\t\t<div class=\"wpr-testimonial-prev-arrow wpr-testimonial-arrow\" id=\"wpr-testimonial-prev-8c7308a\">\r\n\t\t\t\t\t<svg version=\"1.1\" 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\"\/><\/g><\/svg>\t\t\t\t<\/div>\r\n\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e187202 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e187202\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-145fdcb\" data-id=\"145fdcb\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-a372f0a elementor-widget elementor-widget-heading\" data-id=\"a372f0a\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">FAQ\n<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-482515f elementor-widget elementor-widget-eael-adv-accordion\" data-id=\"482515f\" data-element_type=\"widget\" data-widget_type=\"eael-adv-accordion.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t        <div class=\"eael-adv-accordion\" id=\"eael-adv-accordion-482515f\" data-accordion-id=\"482515f\" data-accordion-type=\"accordion\" data-toogle-speed=\"300\">\n    <div class=\"eael-accordion-list\">\n                <div id=\"whata-are-the-prerequisites\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7561\" data-tab=\"1\" role=\"tab\" aria-controls=\"elementor-tab-content-7561\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Whata are the prerequisites<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7561\" class=\"eael-accordion-content clearfix\" data-tab=\"1\" role=\"tabpanel\" aria-labelledby=\"whata-are-the-prerequisites\"><p><p>Digital and anlog design concepts<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"course-materials-shared\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7562\" data-tab=\"2\" role=\"tab\" aria-controls=\"elementor-tab-content-7562\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Course materials shared<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7562\" class=\"eael-accordion-content clearfix\" data-tab=\"2\" role=\"tabpanel\" aria-labelledby=\"course-materials-shared\"><p><ul><li>Session notes<\/li><li>Lab documents with<\/li><li>detailed steps<\/li><li>User guides<\/li><\/ul><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-is-physical-design-in-vlsi\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7563\" data-tab=\"3\" role=\"tab\" aria-controls=\"elementor-tab-content-7563\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What is Physical Design in VLSI?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7563\" class=\"eael-accordion-content clearfix\" data-tab=\"3\" role=\"tabpanel\" aria-labelledby=\"what-is-physical-design-in-vlsi\"><p><p>Physical Design is the backend implementation stage of ASIC design where RTL netlist is converted into a manufacturable layout (GDSII). It includes floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff verification.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-is-covered-in-this-physical-design-training-program\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7564\" data-tab=\"4\" role=\"tab\" aria-controls=\"elementor-tab-content-7564\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What is covered in this Physical Design training program?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7564\" class=\"eael-accordion-content clearfix\" data-tab=\"4\" role=\"tabpanel\" aria-labelledby=\"what-is-covered-in-this-physical-design-training-program\"><p><p>The course covers complete ASIC backend implementation including netlist to GDSII flow, floorplanning, power planning, placement optimization, CTS, routing, Static Timing Analysis (STA), IR Drop analysis, EM checks, and signoff methodology at 14nm technology node.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"which-tools-are-used-during-the-training\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7565\" data-tab=\"5\" role=\"tab\" aria-controls=\"elementor-tab-content-7565\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Which tools are used during the training?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7565\" class=\"eael-accordion-content clearfix\" data-tab=\"5\" role=\"tabpanel\" aria-labelledby=\"which-tools-are-used-during-the-training\"><p><p data-start=\"1299\" data-end=\"1365\">Students get hands-on exposure to industry-standard tools such as:<\/p><ul data-start=\"1366\" data-end=\"1437\"><li data-start=\"1366\" data-end=\"1383\"><p data-start=\"1368\" data-end=\"1383\">Synopsys ICC2<\/p><\/li><li data-start=\"1384\" data-end=\"1403\"><p data-start=\"1386\" data-end=\"1403\">Cadence Innovus<\/p><\/li><li data-start=\"1404\" data-end=\"1437\"><p data-start=\"1406\" data-end=\"1437\">PrimeTime for timing analysis<\/p><\/li><\/ul><p data-start=\"1439\" data-end=\"1529\">These tools are widely used in semiconductor companies for Physical Design implementation.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"is-this-course-suitable-for-freshers\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7566\" data-tab=\"6\" role=\"tab\" aria-controls=\"elementor-tab-content-7566\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Is this course suitable for freshers?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7566\" class=\"eael-accordion-content clearfix\" data-tab=\"6\" role=\"tabpanel\" aria-labelledby=\"is-this-course-suitable-for-freshers\"><p><p data-start=\"1582\" data-end=\"1785\">Yes. The first 2.5 months focus on digital design fundamentals, CMOS basics, ASIC flow, Linux, and TCL scripting to build strong foundational knowledge before moving into advanced backend implementation.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"will-i-work-on-real-time-projects\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7567\" data-tab=\"7\" role=\"tab\" aria-controls=\"elementor-tab-content-7567\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Will I work on real-time projects?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7567\" class=\"eael-accordion-content clearfix\" data-tab=\"7\" role=\"tabpanel\" aria-labelledby=\"will-i-work-on-real-time-projects\"><p><p>Yes. Students implement complete block-level Physical Design projects at 14nm technology node, covering floorplanning to final timing closure and signoff checks.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-is-timing-closure-in-physical-design\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7568\" data-tab=\"8\" role=\"tab\" aria-controls=\"elementor-tab-content-7568\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What is timing closure in Physical Design?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7568\" class=\"eael-accordion-content clearfix\" data-tab=\"8\" role=\"tabpanel\" aria-labelledby=\"what-is-timing-closure-in-physical-design\"><p><p>Timing closure is the process of fixing setup and hold violations to ensure the design meets required timing constraints under different operating conditions. This includes optimization during placement, CTS, and routing stages.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"do-you-cover-ir-drop-and-em-analysis\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7569\" data-tab=\"9\" role=\"tab\" aria-controls=\"elementor-tab-content-7569\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Do you cover IR Drop and EM analysis?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7569\" class=\"eael-accordion-content clearfix\" data-tab=\"9\" role=\"tabpanel\" aria-labelledby=\"do-you-cover-ir-drop-and-em-analysis\"><p><p data-start=\"2335\" data-end=\"2511\">Yes. The course provides overview and practical understanding of IR Drop analysis and Electromigration (EM) checks, which are critical for power integrity and chip reliability.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-is-clock-tree-synthesis-cts\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"75610\" data-tab=\"10\" role=\"tab\" aria-controls=\"elementor-tab-content-75610\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What is Clock Tree Synthesis (CTS)?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-75610\" class=\"eael-accordion-content clearfix\" data-tab=\"10\" role=\"tabpanel\" aria-labelledby=\"what-is-clock-tree-synthesis-cts\"><p><p data-start=\"2562\" data-end=\"2715\">Clock Tree Synthesis is the stage where the clock network is built to ensure balanced clock distribution with minimal skew and latency across the design.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"does-the-course-include-static-timing-analysis-sta\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"75611\" data-tab=\"11\" role=\"tab\" aria-controls=\"elementor-tab-content-75611\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Does the course include Static Timing Analysis (STA)?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-75611\" class=\"eael-accordion-content clearfix\" data-tab=\"11\" role=\"tabpanel\" aria-labelledby=\"does-the-course-include-static-timing-analysis-sta\"><p><p data-start=\"2784\" data-end=\"2927\">Yes. Students learn timing fundamentals and use PrimeTime concepts to analyze setup\/hold violations, timing paths, and optimization strategies.<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-technology-node-is-used-in-projects\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"75612\" data-tab=\"12\" role=\"tab\" aria-controls=\"elementor-tab-content-75612\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What technology node is used in projects?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-75612\" class=\"eael-accordion-content clearfix\" data-tab=\"12\" role=\"tabpanel\" aria-labelledby=\"what-technology-node-is-used-in-projects\"><p><p>The advanced training includes project implementation at 14nm technology node to give exposure to modern semiconductor design challenges.<\/p><\/p><\/div>\n                <\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>physical design training Home > Course physical design training Course Duration: 131 Hours 4.6 Star (Rating) 3000 (Student Enrolled till Now) About Course Demo Videos Course Videos Course Curriculum Benefits of eLearning? Course Instructor About Course VLSI Physical Design Training \u2013 Complete ASIC Backend Implementation Course This 8-month Physical Design training program is a comprehensive, [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"footnotes":""},"class_list":["post-9087","page","type-page","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Vlsi physical Design Training Course<\/title>\n<meta name=\"description\" content=\"Join VLSI Physical Design training in Bangalore and Hyderabad with hands-on tools, real-time projects, and expert-led sessions for career growth.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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