{"id":9302,"date":"2026-03-09T07:32:39","date_gmt":"2026-03-09T07:32:39","guid":{"rendered":"https:\/\/inskill.in\/training\/physical-design-training-copy\/"},"modified":"2026-03-09T08:16:41","modified_gmt":"2026-03-09T08:16:41","slug":"vlsi-design-flow-for-program-managers","status":"publish","type":"page","link":"https:\/\/inskill.in\/training\/vlsi-design-flow-for-program-managers\/","title":{"rendered":"VLSI Design Flow for Program Managers"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"9302\" class=\"elementor elementor-9302\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-c32f84d elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"c32f84d\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-8ab2f2a\" data-id=\"8ab2f2a\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-bf06656 elementor-widget elementor-widget-heading\" data-id=\"bf06656\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h2 class=\"elementor-heading-title elementor-size-default\">VLSI Design Flow for Program Managers<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-50c5ef1 elementor-widget elementor-widget-heading\" data-id=\"50c5ef1\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Home > \nCourse<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-b6b5a0f elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"b6b5a0f\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-13f4440\" data-id=\"13f4440\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-94547bc elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"94547bc\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-inner-column elementor-element elementor-element-7bcfa7c\" data-id=\"7bcfa7c\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-7452ca1 elementor-widget elementor-widget-heading\" data-id=\"7452ca1\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">VLSI Design Flow for Program Managers<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5101cb3 elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"5101cb3\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<link rel=\"stylesheet\" href=\"https:\/\/inskill.in\/training\/wp-content\/plugins\/elementor\/assets\/css\/widget-icon-list.min.css\">\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-calendar-alt\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Course Duration: 35 Hours<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5dc06f7 elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"5dc06f7\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-star\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">4.6 Star (Rating)<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8f3a455 elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"8f3a455\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-user-tag\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">3000 (Student Enrolled till Now)<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-d25cf2d elementor-widget elementor-widget-eael-adv-tabs\" data-id=\"d25cf2d\" data-element_type=\"widget\" data-widget_type=\"eael-adv-tabs.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t        <div id=\"eael-advance-tabs-d25cf2d\" class=\"eael-advance-tabs eael-tabs-horizontal eael-tab-auto-active\" data-tabid=\"d25cf2d\">\n            <div class=\"eael-tabs-nav\">\n                <ul class=\"eael-tab-inline-icon\">\n                                            <li id=\"about-course\" class=\"active-default eael-tab-item-trigger\" aria-selected=\"true\" data-tab=\"1\" role=\"tab\" tabindex=\"0\" aria-controls=\"about-course-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">About Course<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-videos\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"2\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-videos-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Videos<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-curriculum\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"3\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-curriculum-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Curriculum<\/span>                            \n                                                    <\/li>\n                                            <li id=\"benefits-of-elearning\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"4\" role=\"tab\" tabindex=\"-1\" aria-controls=\"benefits-of-elearning-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Benefits of eLearning?<\/span>                            \n                                                    <\/li>\n                                            <li id=\"course-instructor\" class=\"inactive eael-tab-item-trigger\" aria-selected=\"false\" data-tab=\"5\" role=\"tab\" tabindex=\"-1\" aria-controls=\"course-instructor-tab\" aria-expanded=\"false\">\n                            \n                                                        \n                                                            <span class=\"eael-tab-title  title-after-icon\">Course Instructor<\/span>                            \n                                                    <\/li>\n                                    <\/ul>\n            <\/div>\n            \n            <div class=\"eael-tabs-content\">\n\t\t        \n                    <div id=\"about-course-tab\" class=\"clearfix eael-tab-content-item active-default\" data-title-link=\"about-course-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">About Course<\/h5>\n<div class=\"course-list\">\n<div style=\"font-family: 'Segoe UI', Roboto, Arial, sans-serif; line-height: 1.9; color: #333; max-width: 1000px; margin: auto;\">\n\n<h2 style=\"font-size: 30px; font-weight: bold; color: #0a2a66; margin-bottom: 15px;\">VLSI Design Flow for Program Managers \u2013 Semiconductor Project Management Training<\/h2>\n\n<p style=\"font-size: 16px; margin-bottom: 15px;\">\nThe <strong>VLSI Design Flow for Program Managers<\/strong> course is designed to help program managers and technical leaders understand the complete <strong>semiconductor chip development lifecycle<\/strong>. The course introduces the end-to-end <strong>ASIC and SoC design flow from system specification to silicon tape-out<\/strong>, enabling program managers to effectively manage complex <strong>VLSI product development programs<\/strong>.\n<\/p>\n\n<p style=\"font-size: 16px; margin-bottom: 15px;\">\nParticipants gain strong understanding of how different engineering teams such as <strong>RTL designers, verification engineers, physical design engineers, timing engineers, and validation teams<\/strong> collaborate during the chip development lifecycle. The program focuses on <strong>design milestones, cross-team coordination, risk management, tape-out planning, and semiconductor project execution<\/strong>.\n<\/p>\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Course Duration &amp; Structure<\/h3>\n\n<p style=\"font-size: 16px; margin-bottom: 10px;\">\n<strong>Foundation Phase \u2013 2 Weeks<\/strong><br>\nSemiconductor fundamentals and VLSI design flow overview\n<\/p>\n\n<p style=\"font-size: 16px; margin-bottom: 10px;\">\n<strong>Core Phase \u2013 3 Weeks<\/strong><br>\nFrontend and Backend design flow understanding\n<\/p>\n\n<p style=\"font-size: 16px; margin-bottom: 15px;\">\n<strong>Management Phase \u2013 3 Weeks<\/strong><br>\nSemiconductor project planning and program management\n<\/p>\n\n<p style=\"font-size: 16px; margin-bottom: 15px;\">\nTotal Duration: <strong>6\u20138 Weeks Industry-Oriented Training<\/strong>\n<\/p>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Semiconductor &amp; VLSI Fundamentals<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Introduction to semiconductor technology<\/li>\n<li>CMOS fundamentals and integrated circuits<\/li>\n<li>ASIC vs SoC design concepts<\/li>\n<li>Overview of semiconductor product development<\/li>\n<li>Technology nodes and chip manufacturing process<\/li>\n<li>Basic architecture of digital chips<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Complete ASIC Design Flow Overview<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>System specification and chip architecture planning<\/li>\n<li>RTL design and hardware description concepts<\/li>\n<li>Functional verification and simulation methodology<\/li>\n<li>Design synthesis and logic optimization<\/li>\n<li>Physical design implementation flow<\/li>\n<li>Static Timing Analysis (STA) overview<\/li>\n<li>Physical verification (DRC \/ LVS)<\/li>\n<li>Design signoff and tape-out preparation<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Frontend Design Flow<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Chip architecture and microarchitecture planning<\/li>\n<li>RTL development and coding methodologies<\/li>\n<li>Functional verification strategies<\/li>\n<li>Design simulation and debugging<\/li>\n<li>Design for Testability (DFT) concepts<\/li>\n<li>Verification closure and validation<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Backend Implementation Flow<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Logic synthesis and gate-level design<\/li>\n<li>Floorplanning and chip planning concepts<\/li>\n<li>Standard cell placement and optimization<\/li>\n<li>Clock Tree Synthesis (CTS) overview<\/li>\n<li>Routing strategies and congestion analysis<\/li>\n<li>Timing closure and power optimization concepts<\/li>\n<li>Physical verification and signoff methodology<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Semiconductor Manufacturing &amp; Tape-Out<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Wafer fabrication process overview<\/li>\n<li>Technology nodes and advanced chip manufacturing<\/li>\n<li>Packaging and chip assembly process<\/li>\n<li>Post-silicon validation and testing<\/li>\n<li>Product qualification and release<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">VLSI Project &amp; Program Management<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Semiconductor project lifecycle management<\/li>\n<li>ASIC design milestone planning<\/li>\n<li>Engineering resource allocation strategies<\/li>\n<li>Cross-functional team coordination<\/li>\n<li>Risk management in chip development<\/li>\n<li>Tape-out schedule tracking<\/li>\n<li>Design review and milestone management<\/li>\n<li>Stakeholder communication and reporting<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Training Modes Available<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Classroom Training<\/li>\n<li>Live Online Instructor-Led Training<\/li>\n<li>Weekend Batches<\/li>\n<li>Corporate Training Programs<\/li>\n<li>Executive Learning Programs<\/li>\n<\/ul>\n\n<p style=\"font-size: 16px; margin-bottom: 15px;\">\nFlexible training modes allow professionals and managers to learn the <strong>VLSI design lifecycle and semiconductor project execution<\/strong> without interrupting their professional responsibilities.\n<\/p>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Who Should Enroll?<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Program Managers in semiconductor industry<\/li>\n<li>Project Managers handling ASIC development programs<\/li>\n<li>Engineering Managers managing VLSI teams<\/li>\n<li>Technical Leads transitioning to program management roles<\/li>\n<li>Professionals working with chip design and semiconductor products<\/li>\n<\/ul>\n\n\n<h3 style=\"font-size: 22px; font-weight: 600; color: #0f4c81; margin-top: 30px; margin-bottom: 10px;\">Career Benefits<\/h3>\n\n<ul style=\"font-size: 16px; padding-left: 20px; margin-bottom: 20px;\">\n<li>Strong understanding of semiconductor product lifecycle<\/li>\n<li>Ability to manage complex ASIC design programs<\/li>\n<li>Improved coordination between design and verification teams<\/li>\n<li>Better project planning and tape-out readiness tracking<\/li>\n<li>Leadership skills for VLSI engineering program delivery<\/li>\n<\/ul>\n\n<p style=\"font-size: 16px; font-weight: 600; color: #0a2a66;\">\nThis program equips managers with the technical awareness required to successfully lead <strong>ASIC and SoC development programs in semiconductor organizations<\/strong>, ensuring efficient project execution and successful silicon delivery.\n<\/p>\n\n<\/div>\n<\/div>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-videos-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-videos-tab\">\n\t\t\t\t        \t\t\t\t\t        <p>\u00a0<\/p><table style=\"height: 1880px;\" width=\"742\"><tbody><tr><td width=\"46\">Unit Number<\/td><td width=\"242\">Topic<\/td><td width=\"109\">Duration(mins)<\/td><\/tr><tr><td width=\"46\">1<\/td><td width=\"242\">Electronics systems and vlsi flow<\/td><td width=\"109\">18:23<\/td><\/tr><tr><td width=\"46\">2<\/td><td width=\"242\">Usb devices<\/td><td width=\"109\">18:13<\/td><\/tr><tr><td width=\"46\">3<\/td><td width=\"242\">Soc architecture<\/td><td width=\"109\">26:30<\/td><\/tr><tr><td width=\"46\">4<\/td><td width=\"242\">Understanding systems<\/td><td width=\"109\">19:12<\/td><\/tr><tr><td width=\"46\">5<\/td><td width=\"242\">Revision,ms office<\/td><td width=\"109\">24:33<\/td><\/tr><tr><td width=\"46\">6<\/td><td width=\"242\">protocols<\/td><td width=\"109\">47:52<\/td><\/tr><tr><td width=\"46\">7<\/td><td width=\"242\">Registers<\/td><td width=\"109\">31:01<\/td><\/tr><tr><td width=\"46\">8<\/td><td width=\"242\">Soc,octa core processors<\/td><td width=\"109\">30:56<\/td><\/tr><tr><td width=\"46\">9<\/td><td width=\"242\">Dft,use case of driver<\/td><td width=\"109\">17:45<\/td><\/tr><tr><td width=\"46\">10<\/td><td width=\"242\">vlsi,pvt<\/td><td width=\"109\">18:34<\/td><\/tr><tr><td width=\"46\">11<\/td><td width=\"242\">ASIC\/FPGA<\/td><td width=\"109\">49:51<\/td><\/tr><tr><td width=\"46\">12<\/td><td width=\"242\">Power verification<\/td><td width=\"109\">22:00<\/td><\/tr><tr><td width=\"46\">13<\/td><td width=\"242\">ASIC team distribution<\/td><td width=\"109\">32:45<\/td><\/tr><tr><td width=\"46\">14<\/td><td width=\"242\">Asic Design flow<\/td><td width=\"109\">38:38<\/td><\/tr><tr><td width=\"46\">15<\/td><td width=\"242\">Factors driving vlsi flow<\/td><td width=\"109\">20:40<\/td><\/tr><tr><td width=\"46\">16<\/td><td width=\"242\">Memory acess latency<\/td><td width=\"109\">34:39<\/td><\/tr><tr><td width=\"46\">17<\/td><td width=\"242\">Power<\/td><td width=\"109\">39:35<\/td><\/tr><tr><td width=\"46\">18<\/td><td width=\"242\">Upf,fetention logic<\/td><td width=\"109\">22:34<\/td><\/tr><tr><td width=\"46\">19<\/td><td width=\"242\">Vlsi front end domain<\/td><td width=\"109\">30:16<\/td><\/tr><tr><td width=\"46\">20<\/td><td width=\"242\">Clock Domain,rtl integeration flow<\/td><td width=\"109\">25:12<\/td><\/tr><tr><td width=\"46\">21<\/td><td width=\"242\">Functional verification,lint anylsis<\/td><td width=\"109\">49:01<\/td><\/tr><tr><td width=\"46\">22<\/td><td width=\"242\">VLSI back end domain flow<\/td><td width=\"109\">31:44<\/td><\/tr><tr><td width=\"46\">23<\/td><td width=\"242\">Place and route<\/td><td width=\"109\">17:57<\/td><\/tr><tr><td width=\"46\">24<\/td><td width=\"242\">Tools used in asic design flow<\/td><td width=\"109\">30:06<\/td><\/tr><tr><td width=\"46\">25<\/td><td width=\"242\">Significance of transistor ih HW<\/td><td width=\"109\">16:34<\/td><\/tr><tr><td width=\"46\">26<\/td><td width=\"242\">FPGA design flow<\/td><td width=\"109\">49:09<\/td><\/tr><tr><td width=\"46\">27<\/td><td width=\"242\">TLC coding<\/td><td width=\"109\">19:44<\/td><\/tr><tr><td width=\"46\">28<\/td><td width=\"242\">Smulation (tool explination)<\/td><td width=\"109\">27:29<\/td><\/tr><tr><td width=\"46\">29<\/td><td width=\"242\">STA,PVT corner<\/td><td width=\"109\">51:12<\/td><\/tr><tr><td width=\"46\">30<\/td><td width=\"242\">Lint<\/td><td width=\"109\">29:09<\/td><\/tr><tr><td width=\"46\">31<\/td><td width=\"242\">UPF<\/td><td width=\"109\">41:52<\/td><\/tr><tr><td width=\"46\">32<\/td><td width=\"242\">SYNTHESIS<\/td><td width=\"109\">35:27<\/td><\/tr><tr><td width=\"46\">33<\/td><td width=\"242\">Working with tool<\/td><td width=\"109\">34:26<\/td><\/tr><tr><td width=\"46\">34<\/td><td width=\"242\">SYNTHESIS flow<\/td><td width=\"109\">01:32:21<\/td><\/tr><tr><td width=\"46\">35<\/td><td width=\"242\">DFT<\/td><td width=\"109\">33:19<\/td><\/tr><tr><td width=\"46\">36<\/td><td width=\"242\">SCAN chain operation<\/td><td width=\"109\">26:26<\/td><\/tr><tr><td width=\"46\">37<\/td><td width=\"242\">measure so explation demonstration<\/td><td width=\"109\">01:28:59<\/td><\/tr><tr><td width=\"46\">38<\/td><td width=\"242\">PD flow<\/td><td width=\"109\">27:51<\/td><\/tr><tr><td width=\"46\">39<\/td><td width=\"242\">steps<\/td><td width=\"109\">29:58<\/td><\/tr><tr><td width=\"46\">40<\/td><td width=\"242\">what is floorplan<\/td><td width=\"109\">57:05<\/td><\/tr><tr><td width=\"46\">41<\/td><td width=\"242\">Port placement<\/td><td width=\"109\">28:03<\/td><\/tr><tr><td width=\"46\">42<\/td><td width=\"242\">Macro placement guidelines<\/td><td width=\"109\">44:14<\/td><\/tr><tr><td width=\"46\">43<\/td><td width=\"242\">Physical only cell<\/td><td width=\"109\">30:34<\/td><\/tr><tr><td width=\"46\">44<\/td><td width=\"242\">power planning<\/td><td width=\"109\">48:04<\/td><\/tr><tr><td width=\"46\">45<\/td><td width=\"242\">ASIC PD flow<\/td><td width=\"109\">44:49<\/td><\/tr><tr><td width=\"46\">46<\/td><td width=\"242\">p1 continution<\/td><td width=\"109\">38:50<\/td><\/tr><tr><td width=\"46\">47<\/td><td width=\"242\">p2 continution, what is placement<\/td><td width=\"109\">34:34<\/td><\/tr><tr><td width=\"46\">48<\/td><td width=\"242\">checks after placements<\/td><td width=\"109\">53:57<\/td><\/tr><tr><td width=\"46\">49<\/td><td width=\"242\">clock tree synthesis<\/td><td width=\"109\">01:03:46<\/td><\/tr><tr><td width=\"46\">50<\/td><td width=\"242\">routing<\/td><td width=\"109\">42:36<\/td><\/tr><tr><td width=\"46\">51<\/td><td width=\"242\">DRC flow<\/td><td width=\"109\">29:21<\/td><\/tr><tr><td width=\"46\">52<\/td><td width=\"242\">STA<\/td><td width=\"109\">25:36<\/td><\/tr><tr><td width=\"46\">53<\/td><td width=\"242\">Writing Out SDC<\/td><td width=\"109\">35:06<\/td><\/tr><tr><td width=\"46\">54<\/td><td width=\"242\">Violations<\/td><td width=\"109\">15:35<\/td><\/tr><tr><td width=\"46\">55<\/td><td width=\"242\">AMS IC DESIGN<\/td><td width=\"109\">30:26<\/td><\/tr><\/tbody><\/table><p>\u00a0<\/p>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-curriculum-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-curriculum-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Curriculum<\/h5><p>\t\t\t\t\t\t\t<h3 style=\"margin-bottom:20px;display:block;width:100%;margin-top:10px\">VLSI Design Flow for Program Managers <\/h3>\r\n\t\t\t\t\t\t<style>\r\n\t\t\t\t<style>\r\n#wpsm_accordion_9309 .wpsm_panel-heading{\r\n\tpadding:0px !important;\r\n}\r\n#wpsm_accordion_9309 .wpsm_panel-title {\r\n\tmargin:0px !important; \r\n\ttext-transform:none !important;\r\n\tline-height: 1 !important;\r\n}\r\n#wpsm_accordion_9309 .wpsm_panel-title a{\r\n\ttext-decoration:none;\r\n\toverflow:hidden;\r\n\tdisplay:block;\r\n\tpadding:0px;\r\n\tfont-size: 18px !important;\r\n\tfont-family: Open Sans !important;\r\n\tcolor:#000000 !important;\r\n\tborder-bottom:0px !important;\r\n}\r\n\r\n#wpsm_accordion_9309 .wpsm_panel-title a:focus {\r\noutline: 0px !important;\r\n}\r\n\r\n#wpsm_accordion_9309 .wpsm_panel-title a:hover, #wpsm_accordion_9309 .wpsm_panel-title a:focus {\r\n\tcolor:#000000 !important;\r\n}\r\n#wpsm_accordion_9309 .acc-a{\r\n\tcolor: #000000 !important;\r\n\tbackground-color:#e8e8e8 !important;\r\n\tborder-color: #ddd;\r\n}\r\n#wpsm_accordion_9309 .wpsm_panel-default > .wpsm_panel-heading{\r\n\tcolor: #000000 !important;\r\n\tbackground-color: #e8e8e8 !important;\r\n\tborder-color: #e8e8e8 !important;\r\n\tborder-top-left-radius: 0px;\r\n\tborder-top-right-radius: 0px;\r\n}\r\n#wpsm_accordion_9309 .wpsm_panel-default {\r\n\t\tborder:1px solid transparent !important;\r\n\t}\r\n#wpsm_accordion_9309 {\r\n\tmargin-bottom: 20px;\r\n\toverflow: hidden;\r\n\tfloat: none;\r\n\twidth: 100%;\r\n\tdisplay: block;\r\n}\r\n#wpsm_accordion_9309 .ac_title_class{\r\n\tdisplay: block;\r\n\tpadding-top: 12px;\r\n\tpadding-bottom: 12px;\r\n\tpadding-left: 15px;\r\n\tpadding-right: 15px;\r\n}\r\n#wpsm_accordion_9309  .wpsm_panel {\r\n\toverflow:hidden;\r\n\t-webkit-box-shadow: 0 0px 0px rgba(0, 0, 0, .05);\r\n\tbox-shadow: 0 0px 0px rgba(0, 0, 0, .05);\r\n\t\tborder-radius: 4px;\r\n\t}\r\n#wpsm_accordion_9309  .wpsm_panel + .wpsm_panel {\r\n\t\tmargin-top: 5px;\r\n\t}\r\n#wpsm_accordion_9309  .wpsm_panel-body{\r\n\tbackground-color:#ffffff !important;\r\n\tcolor:#000000 !important;\r\n\tborder-top-color: #e8e8e8 !important;\r\n\tfont-size:16px !important;\r\n\tfont-family: Open Sans !important;\r\n\toverflow: hidden;\r\n\t\tborder: 2px solid #e8e8e8 !important;\r\n\t}\r\n\r\n#wpsm_accordion_9309 .ac_open_cl_icon{\r\n\tbackground-color:#e8e8e8 !important;\r\n\tcolor: #000000 !important;\r\n\tfloat:right !important;\r\n\tpadding-top: 12px !important;\r\n\tpadding-bottom: 12px !important;\r\n\tline-height: 1.0 !important;\r\n\tpadding-left: 15px !important;\r\n\tpadding-right: 15px !important;\r\n\tdisplay: inline-block !important;\r\n}\r\n\r\n\t\t\t\r\n\t\t\t<\/style>\t\r\n\t\t\t<\/style>\r\n\t\t\t<div class=\"wpsm_panel-group\" id=\"wpsm_accordion_9309\" >\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse1\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-minus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tElectronics Systems &amp; VLSI Fundamentals\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse1\" class=\"wpsm_panel-collapse collapse in\"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>Electronics Systems and VLSI Flow<\/li>\r\n<li>Understanding Electronic Systems<\/li>\r\n<li>Factors Driving VLSI Design Flow<\/li>\r\n<li>Significance of Transistors in Hardware<\/li>\r\n<li>VLSI Process Variations (PVT)<\/li>\r\n<li>ASIC vs FPGA Overview<\/li>\r\n<li>Revision Session and Basic Tools Overview<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse2\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tSystem Architecture &amp; SoC Design\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse2\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>System on Chip (SoC) Architecture<\/li>\r\n<li>Octa Core Processor Architecture<\/li>\r\n<li>Registers and Data Storage Concepts<\/li>\r\n<li>Memory Access Latency<\/li>\r\n<li>USB Devices and Hardware Interfaces<\/li>\r\n<li>Hardware Communication Protocols<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse3\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tASIC Development Teams &amp; Industry Workflow\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse3\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>ASIC Team Distribution and Roles<\/li>\r\n<li>VLSI Frontend Domain Overview<\/li>\r\n<li>VLSI Backend Domain Overview<\/li>\r\n<li>Tools Used in ASIC Design Flow<\/li>\r\n<li>Working with Industry Tools<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse4\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tRTL Design &amp; Frontend Development\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse4\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>RTL Integration Flow<\/li>\r\n<li>Clock Domain Concepts<\/li>\r\n<li>Functional Verification<\/li>\r\n<li>Lint Analysis<\/li>\r\n<li>RTL Simulation Concepts<\/li>\r\n<li>Simulation Tool Explanation<\/li>\r\n<li>TCL Coding for Design Automation<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse5\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tSynthesis &amp; Static Timing Analysis\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse5\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>Synthesis Fundamentals<\/li>\r\n<li>Synthesis Design Flow<\/li>\r\n<li>Static Timing Analysis (STA)<\/li>\r\n<li>PVT Corner Analysis<\/li>\r\n<li>Writing SDC Constraints<\/li>\r\n<li>Timing Violations and Debugging<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse6\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPower Verification &amp; Low Power Design\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse6\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>Power Analysis in VLSI<\/li>\r\n<li>Power Verification Concepts<\/li>\r\n<li>UPF (Unified Power Format)<\/li>\r\n<li>Retention Logic<\/li>\r\n<li>Low Power Design Methodologies<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse7\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tDesign for Testability (DFT)\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse7\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>Introduction to Design for Testability<\/li>\r\n<li>DFT Concepts in ASIC<\/li>\r\n<li>Scan Chain Operation<\/li>\r\n<li>DFT Implementation Flow<\/li>\r\n<li>Measurement and Testing Demonstration<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse8\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tPlacement, Clock Tree &amp; Routing\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse8\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>Placement Concepts<\/li>\r\n<li>Placement Optimization<\/li>\r\n<li>Checks After Placement<\/li>\r\n<li>Clock Tree Synthesis (CTS)<\/li>\r\n<li>Routing in Physical Design<\/li>\r\n<li>Design Rule Check (DRC) Flow<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<!-- Inner panel Start -->\r\n\t\t\t\t\t<div class=\"wpsm_panel wpsm_panel-default\">\r\n\t\t\t\t\t\t<div class=\"wpsm_panel-heading\" role=\"tab\" >\r\n\t\t\t\t\t\t  <h4 class=\"wpsm_panel-title\">\r\n\t\t\t\t\t\t\t<a  class=\"collapsed\"  data-toggle=\"collapse\" data-parent=\"#wpsm_accordion_9309 \" href=\"javascript:void(0)\" data-target=\"#ac_9309_collapse9\" onclick=\"do_resize()\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"ac_open_cl_icon fa fa-plus\"><\/span>\r\n\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t \r\n\t\t\t\t\t\t\t\t<span class=\"ac_title_class\">\r\n\t\t\t\t\t\t\t\t\tAdvanced VLSI Design Concepts\t\t\t\t\t\t\t\t<\/span>\r\n\t\t\t\t\t\t\t<\/a>\r\n\t\t\t\t\t\t  <\/h4>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t<div id=\"ac_9309_collapse9\" class=\"wpsm_panel-collapse collapse \"  >\r\n\t\t\t\t\t\t  <div class=\"wpsm_panel-body\">\r\n\t\t\t\t\t\t\t<ul>\r\n<li>FPGA Design Flow<\/li>\r\n<li>Analog Mixed Signal (AMS) IC Design<\/li>\r\n<li>Post Layout Timing Analysis<\/li>\r\n<li>Final Design Signoff Concepts<\/li>\r\n<\/ul>\t\t\t\t\t\t  <\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<\/div>\r\n\t\t\t\t\t<!-- Inner panel End -->\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\r\n<script type=\"text\/javascript\">\r\n\t\r\n\t\tfunction do_resize(){\r\n\r\n\t\t\tvar width=jQuery( '.wpsm_panel .wpsm_panel-body iframe' ).width();\r\n\t\t\tvar height=jQuery( '.wpsm_panel .wpsm_panel-body iframe' ).height();\r\n\r\n\t\t\tvar toggleSize = true;\r\n\t\t\tjQuery('iframe').animate({\r\n\t\t\t    width: toggleSize ? width : 640,\r\n\t\t\t    height: toggleSize ? height : 360\r\n\t\t\t  }, 250);\r\n\r\n\t\t\t  toggleSize = !toggleSize;\r\n\t\t}\r\n\t\t\r\n<\/script>\t<\/p>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"benefits-of-elearning-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"benefits-of-elearning-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Benefits of eLearning?<\/h5><div class=\"course-list\"><ul><li>Access to the Instructor - Ask questions to the Instructor who taught the course<\/li><li>Available 24\/7 - VLSIGuru eLearning courses are available when and where you need them<\/li><li>Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready<\/li><\/ul><\/div>\t\t\t\t                            <\/div>\n\t\t        \n                    <div id=\"course-instructor-tab\" class=\"clearfix eael-tab-content-item inactive\" data-title-link=\"course-instructor-tab\">\n\t\t\t\t        \t\t\t\t\t        <h5 class=\"card-title\">Course Instructor<\/h5><div class=\"course-list\"><ul><li>Sreenivas Reddy \u2014 Founder, VLSIGuru<\/li><\/ul><\/div>\t\t\t\t                            <\/div>\n\t\t                    <\/div>\n        <\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-3280dea\" data-id=\"3280dea\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-d661710 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"d661710\" 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data-settings=\"{&quot;youtube_url&quot;:&quot;https:\\\/\\\/youtu.be\\\/xvmFO85CooQ&quot;,&quot;show_image_overlay&quot;:&quot;yes&quot;,&quot;image_overlay&quot;:{&quot;url&quot;:&quot;https:\\\/\\\/inskill.in\\\/training\\\/wp-content\\\/uploads\\\/2023\\\/03\\\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg&quot;,&quot;id&quot;:485,&quot;size&quot;:&quot;&quot;,&quot;alt&quot;:&quot;&quot;,&quot;source&quot;:&quot;library&quot;},&quot;lightbox&quot;:&quot;yes&quot;,&quot;video_type&quot;:&quot;youtube&quot;,&quot;controls&quot;:&quot;yes&quot;}\" data-widget_type=\"video.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-video .elementor-widget-container{overflow:hidden;transform:translateZ(0)}.elementor-widget-video .elementor-wrapper iframe,.elementor-widget-video .elementor-wrapper video{height:100%;width:100%;border:none;background-color:#000}.elementor-widget-video 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data-e-action-hash=\"#elementor-action%3Aaction%3Dlightbox%26settings%3DeyJ0eXBlIjoidmlkZW8iLCJ2aWRlb1R5cGUiOiJ5b3V0dWJlIiwidXJsIjoiaHR0cHM6XC9cL3d3dy55b3V0dWJlLmNvbVwvZW1iZWRcL3h2bUZPODVDb29RP2ZlYXR1cmU9b2VtYmVkJnN0YXJ0JmVuZCZ3bW9kZT1vcGFxdWUmbG9vcD0wJmNvbnRyb2xzPTEmbXV0ZT0wJnJlbD0wJm1vZGVzdGJyYW5kaW5nPTAiLCJtb2RhbE9wdGlvbnMiOnsiaWQiOiJlbGVtZW50b3ItbGlnaHRib3gtOTBhYTM2OCIsImVudHJhbmNlQW5pbWF0aW9uIjoiIiwiZW50cmFuY2VBbmltYXRpb25fdGFibGV0IjoiIiwiZW50cmFuY2VBbmltYXRpb25fbW9iaWxlIjoiIiwidmlkZW9Bc3BlY3RSYXRpbyI6IjE2OSJ9fQ%3D%3D\">\n\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"427\" height=\"360\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg\" class=\"attachment-full size-full wp-image-485\" alt=\"\" srcset=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1.jpg 427w, https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/03\/360_F_41684575_9WPteW8HOsDqlLoXyo4faqas32pBpZQp-1-300x253.jpg 300w\" sizes=\"auto, (max-width: 427px) 100vw, 427px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-5b12bfa elementor-widget elementor-widget-wpr-elementor-template\" data-id=\"5b12bfa\" data-element_type=\"widget\" data-widget_type=\"wpr-elementor-template.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div data-elementor-type=\"section\" data-elementor-id=\"511\" class=\"elementor elementor-511\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e1113af elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e1113af\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-0269498\" data-id=\"0269498\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-8885478 elementor-align-center elementor-widget__width-initial opopii elementor-widget elementor-widget-button\" data-id=\"8885478\" data-element_type=\"widget\" data-widget_type=\"button.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-button-wrapper\">\n\t\t\t<a href=\"https:\/\/inskill.in\/online\/course_enrol.php\" class=\"elementor-button-link elementor-button elementor-size-lg\" role=\"button\">\n\t\t\t\t\t\t<span class=\"elementor-button-content-wrapper\">\n\t\t\t\t\t\t<span class=\"elementor-button-text\">ENROLL NOW<\/span>\n\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t<span class=\"wpr-template-edit-btn\" data-permalink=\"https:\/\/inskill.in\/training\/?elementor_library=button\">Edit Template<\/span>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-75b71e7 elementor-widget elementor-widget-wpr-elementor-template\" data-id=\"75b71e7\" data-element_type=\"widget\" data-widget_type=\"wpr-elementor-template.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div data-elementor-type=\"section\" data-elementor-id=\"500\" class=\"elementor elementor-500\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-bb3a73c elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"bb3a73c\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-inner-column elementor-element elementor-element-14950a6\" data-id=\"14950a6\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-186e1a84 elementor-widget elementor-widget-heading\" data-id=\"186e1a84\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Course Highlights<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-1246868c elementor-widget__width-auto elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-icon-list\" data-id=\"1246868c\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-user-secret\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">1-1 mentor support<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"fas fa-user-injured\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Mentor guidance support for assignments<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-compass\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Multiple mock interviews<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-icon\">\n\t\t\t\t\t\t\t<i aria-hidden=\"true\" class=\"far fa-clipboard\"><\/i>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Dedicated live support sessions over weekends<\/span>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t<span class=\"wpr-template-edit-btn\" data-permalink=\"https:\/\/inskill.in\/training\/?elementor_library=course_highlights\">Edit Template<\/span>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-91fa43f elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"91fa43f\" data-element_type=\"section\" data-settings=\"{&quot;background_background&quot;:&quot;slideshow&quot;,&quot;background_slideshow_gallery&quot;:[{&quot;id&quot;:438,&quot;url&quot;:&quot;https:\\\/\\\/inskill.in\\\/training\\\/wp-content\\\/uploads\\\/2023\\\/02\\\/vlsi-img.jpg&quot;}],&quot;background_slideshow_loop&quot;:&quot;yes&quot;,&quot;background_slideshow_slide_duration&quot;:5000,&quot;background_slideshow_slide_transition&quot;:&quot;fade&quot;,&quot;background_slideshow_transition_duration&quot;:500}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-c8dece7\" data-id=\"c8dece7\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e8d88d3 elementor-widget elementor-widget-heading\" data-id=\"e8d88d3\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<p class=\"elementor-heading-title elementor-size-default\">TESTIMONIALS<\/p>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-948db1c elementor-widget elementor-widget-heading\" data-id=\"948db1c\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">What Our Students Says About Inskill\n<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8c7308a wpr-testimonial-slider-columns-2 wpr-testimonial-slider-columns--tablet2 wpr-testimonial-slider-columns--mobile1 wpr-testimonial-rating-style_2 wpr-testimonial-triangle-yes wpr-testimonial-meta-position-bottom wpr-testimonial-meta-align-center wpr-testimonial-image-position-center elementor-widget elementor-widget-wpr-testimonial\" data-id=\"8c7308a\" data-element_type=\"widget\" data-settings=\"{&quot;testimonial_amount&quot;:2,&quot;testimonial_amount_tablet&quot;:2,&quot;testimonial_amount_mobile&quot;:1,&quot;testimonial_slides_to_scroll&quot;:2,&quot;testimonial_loop&quot;:&quot;yes&quot;}\" data-widget_type=\"wpr-testimonial.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"wpr-testimonial-carousel-wrap\">\r\n\t\t\t\r\n\t\t\t<div class=\"wpr-testimonial-carousel\" dir=\"ltr\" data-slick=\"{&quot;rtl&quot;:false,&quot;infinite&quot;:true,&quot;speed&quot;:700,&quot;arrows&quot;:true,&quot;dots&quot;:true,&quot;autoplay&quot;:false,&quot;autoplaySpeed&quot;:0,&quot;pauseOnHover&quot;:&quot;&quot;,&quot;prevArrow&quot;:&quot;#wpr-testimonial-prev-8c7308a&quot;,&quot;nextArrow&quot;:&quot;#wpr-testimonial-next-8c7308a&quot;,&quot;sliderSlidesToScroll&quot;:2}\" data-slide-effect=\"slide\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-c1659f3 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img1.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">ONKAR JOSHI <\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-6\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.<br \/>The admins are very much co-operative and understandable and help you throughout the course.<br \/>The concepts taught are in a very simplified manner and every lecture is recorded.<br \/>Very much satisfied will recommend to any VLSI enthusiast<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">7 Days Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-ee54814 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img2.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Uday G R<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-8\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>VLSIGURU training institute is one of the best training institute for VLSI domain.<br \/>They offer best courses for a very low and affordable prices.<br \/>I took e-learning courses, the course content and materials are well planned according to the industry requirements.<br \/>Their lectures are very detailed and cover all the concepts.<br \/>The projects and assignments they give are helpful in cracking a job.<br \/>The admin teams is very supportive all the time. I would definitely recommend to others<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">10.04.2018<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-433c82d elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img4.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Vinutha M B<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-7\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I have taken training at VLSIGURU for Design and functional verification course through online, <br \/>where i got more practical knowledge then usual syllabuses.<br \/>I was very much satisfied learning at this training institute. <br \/>Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience <br \/>which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period. <br \/>every sessions recorded and can be accessed through their website when required. <br \/>The institute also provided hands-on experience with the required tools and provide online access as well. <br \/>This institute has highly well experienced real time working professionals as trainers. <br \/>thanks to VLSIGURU institute.<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">5 Month Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<div class=\"wpr-testimonial-item elementor-repeater-item-e67c709 elementor-clearfix\">\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta elementor-clearfix\">\r\n\t\t\t\t\t\t\t\t<div class=\"wpr-testimonial-meta-inner\">\r\n\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t<div class=\"wpr-testimonial-image\">\r\n\t\t\t\t<img decoding=\"async\" src=\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2023\/02\/tesi-img5.png\" alt=\"\">\r\n\t\t\t<\/div>\r\n\t\t\r\n\t\t\t\r\n\t\t<div class=\"wpr-testimonial-meta-content-wrap\">\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\r\n\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t\t\t\t\t\r\n\t\t<div class=\"wpr-testimonial-content-wrap\">\r\n\t\t\t<div class=\"wpr-testimonial-content-inner\">\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-title\">Beulah Grace<\/div>\r\n\t\t\t\r\n\t\t\t\t\t\t\t\t\r\n\r\n\t\t\t<div class=\"wpr-testimonial-rating\">\r\n\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-full\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\t\t\t\t\t\t\t\t\t<i class=\"wpr-rating-icon-6\">&#9734;<\/i>\r\n\t\t\t\t\t     \t\r\n\t     \t\t\t\t<\/div>\r\n\r\n\t\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-content\">\r\n\t\t\t\t\t\r\n\t\t\t\t\t<p><p>I have taken training at VLSIGURU for Design and Verification course through online. <br \/>They have very experienced faculty with industrial knowledge. <br \/>The trainers explained every concept from the very basic to core concepts with good explanation. <br \/>Every doubt has been clarified with patience and in detail. <br \/>Every session os recorded and can be accessed through their website when required. <br \/>The institute also provided hands-on experience with the required tools and provided online access as well. <br \/>VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts. <br \/>Interview preparation sessions has also been conducted along with mock interviews and training sessions.<br \/>It is the best institute to gain knowledge in core domain with affordable prices. <br \/>I Thank VLSIGURU for helping me to gain knowledge in the core domain.<\/p><\/p>\r\n\t\t\t\t<\/div>\r\n\t\t\t\r\n\t\t\t\r\n\t\t\t\t\t\t\t<div class=\"wpr-testimonial-date\">6 Month Ago<\/div>\r\n\t\t\t\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\r\n\t\t\t\t\t\t\t\r\n\t\t\t\t\t\t<\/div>\r\n\t\t\t\t\t\t\t\t\t<\/div>\r\n\r\n\t\t\t<div class=\"wpr-testimonial-controls\">\r\n\t\t\t\t<div class=\"wpr-testimonial-dots\"><\/div>\r\n\t\t\t<\/div>\r\n\r\n\t\t\t<div class=\"wpr-testimonial-arrow-container\">\r\n\t\t\t\t<div class=\"wpr-testimonial-prev-arrow wpr-testimonial-arrow\" id=\"wpr-testimonial-prev-8c7308a\">\r\n\t\t\t\t\t<svg version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" x=\"0px\" y=\"0px\" viewBox=\"0 0 283.4 512\" style=\"enable-background:new 0 0 283.4 512;\" xml:space=\"preserve\"><g><polygon class=\"st0\" points=\"54.5,256.3 283.4,485.1 256.1,512.5 0,256.3 0,256.3 27.2,229 256.1,0 283.4,27.4 \"\/><\/g><\/svg>\t\t\t\t<\/div>\r\n\t\t\t\t<div class=\"wpr-testimonial-next-arrow wpr-testimonial-arrow\" id=\"wpr-testimonial-next-8c7308a\">\r\n\t\t\t\t\t<svg version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" x=\"0px\" y=\"0px\" viewBox=\"0 0 283.4 512\" style=\"enable-background:new 0 0 283.4 512;\" xml:space=\"preserve\"><g><polygon class=\"st0\" points=\"54.5,256.3 283.4,485.1 256.1,512.5 0,256.3 0,256.3 27.2,229 256.1,0 283.4,27.4 \"\/><\/g><\/svg>\t\t\t\t<\/div>\r\n\t\t\t<\/div>\r\n\t\t<\/div>\r\n\r\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e187202 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e187202\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-145fdcb\" data-id=\"145fdcb\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-a372f0a elementor-widget elementor-widget-heading\" data-id=\"a372f0a\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">FAQ\n<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-482515f elementor-widget elementor-widget-eael-adv-accordion\" data-id=\"482515f\" data-element_type=\"widget\" data-widget_type=\"eael-adv-accordion.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t        <div class=\"eael-adv-accordion\" id=\"eael-adv-accordion-482515f\" data-accordion-id=\"482515f\" data-accordion-type=\"accordion\" data-toogle-speed=\"300\">\n    <div class=\"eael-accordion-list\">\n                <div id=\"whata-are-the-prerequisites\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7561\" data-tab=\"1\" role=\"tab\" aria-controls=\"elementor-tab-content-7561\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Whata are the prerequisites<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7561\" class=\"eael-accordion-content clearfix\" data-tab=\"1\" role=\"tabpanel\" aria-labelledby=\"whata-are-the-prerequisites\"><p><p>Digital and anlog design concepts<\/p><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"course-materials-shared\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7562\" data-tab=\"2\" role=\"tab\" aria-controls=\"elementor-tab-content-7562\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">Course materials shared<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7562\" class=\"eael-accordion-content clearfix\" data-tab=\"2\" role=\"tabpanel\" aria-labelledby=\"course-materials-shared\"><p><ul><li>Session notes<\/li><li>Lab documents with<\/li><li>detailed steps<\/li><li>User guides<\/li><\/ul><\/p><\/div>\n                <\/div><div class=\"eael-accordion-list\">\n                <div id=\"what-is-physical-design-in-vlsi\" class=\"elementor-tab-title eael-accordion-header\" tabindex=\"7563\" data-tab=\"3\" role=\"tab\" aria-controls=\"elementor-tab-content-7563\"><span class=\"eael-advanced-accordion-icon-closed\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-plus\"><\/i><\/span><span class=\"eael-advanced-accordion-icon-opened\"><i aria-hidden=\"true\" class=\"fa-accordion-icon fas fa-minus\"><\/i><\/span><span class=\"eael-accordion-tab-title\">What is Physical Design in VLSI?<\/span><i aria-hidden=\"true\" class=\"fa-toggle fas fa-angle-right\"><\/i><\/div><div id=\"elementor-tab-content-7563\" class=\"eael-accordion-content clearfix\" data-tab=\"3\" role=\"tabpanel\" aria-labelledby=\"what-is-physical-design-in-vlsi\"><p><p>Physical Design is the backend implementation stage of ASIC design where RTL netlist is converted into a manufacturable layout (GDSII). It includes floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff verification.<\/p><\/p><\/div>\n                <\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>VLSI Design Flow for Program Managers Home > Course VLSI Design Flow for Program Managers Course Duration: 35 Hours 4.6 Star (Rating) 3000 (Student Enrolled till Now) About Course Course Videos Course Curriculum Benefits of eLearning? Course Instructor About Course VLSI Design Flow for Program Managers \u2013 Semiconductor Project Management Training The VLSI Design Flow [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"footnotes":""},"class_list":["post-9302","page","type-page","status-publish","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>VLSI Design Flow for Program Managers<\/title>\n<meta name=\"description\" content=\"Learn the complete VLSI design flow from specification to tape-out in this course designed for program managers. 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