{"id":10102,"date":"2026-08-28T11:14:28","date_gmt":"2026-08-28T11:14:28","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10102"},"modified":"2026-08-25T11:16:07","modified_gmt":"2026-08-25T11:16:07","slug":"how-to-avoid-inferred-latches-in-rtl-design","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/how-to-avoid-inferred-latches-in-rtl-design\/","title":{"rendered":"How to Avoid Inferred Latches in RTL Design"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10102\" class=\"elementor elementor-10102\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-69c7361 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"69c7361\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-292f29d\" data-id=\"292f29d\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e8b5782 elementor-widget elementor-widget-text-editor\" data-id=\"e8b5782\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">Writing RTL that synthesizes into the hardware you actually intended is one of the most important skills for a digital design engineer. A few lines of incomplete Verilog can be enough to create hardware that was never part of the original design plan.<\/span><\/p><p><span style=\"font-weight: 400;\">One common example is unintended latch inference.<\/span><\/p><p><span style=\"font-weight: 400;\">Latches are not inherently bad. They are legitimate storage elements and are used deliberately in certain designs. The problem occurs when a latch appears in RTL accidentally because a combinational block does not assign an output under every possible condition.<\/span><\/p><p><span style=\"font-weight: 400;\">For beginners, latch inference can seem confusing because the RTL may look perfectly reasonable during simulation. The synthesis tool, however, interprets the missing assignment as a requirement to preserve the previous value. That behavior requires storage, so a latch is inferred.<\/span><\/p><p><span style=\"font-weight: 400;\">This article explains why inferred latches occur, how to recognize the coding patterns that cause them, and practical ways to write cleaner, predictable RTL.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is an Inferred Latch?<\/span><\/h3><p><span style=\"font-weight: 400;\">A latch is a level-sensitive storage element. Unlike a flip-flop, which normally updates at a clock edge, a latch can allow its output to follow its input while an enable condition is active and retain its previous value when that condition is inactive.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider this simple RTL:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (en)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">At first glance, this appears to mean:<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">en<\/span><span style=\"font-weight: 400;\"> is high, assign <\/span><span style=\"font-weight: 400;\">data<\/span><span style=\"font-weight: 400;\"> to <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">But what should happen when <\/span><span style=\"font-weight: 400;\">en<\/span><span style=\"font-weight: 400;\"> is low?<\/span><\/p><p><span style=\"font-weight: 400;\">There is no assignment to <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore, the hardware must somehow remember the previous value of <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\">. Synthesis can implement that behavior using a latch.<\/span><\/p><p><span style=\"font-weight: 400;\">The corrected combinational version could be:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (en)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Now <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\"> receives a value whether <\/span><span style=\"font-weight: 400;\">en<\/span><span style=\"font-weight: 400;\"> is 1 or 0. No storage is required.<\/span><\/p><p><span style=\"font-weight: 400;\">Another common solution is to provide a default assignment:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = 1&#8217;b0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (en)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The second style becomes particularly useful when a combinational block contains several conditions.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why Do Latches Get Inferred?<\/span><\/h3><p><span style=\"font-weight: 400;\">The basic reason is simple: <\/span><b>an output is not assigned on every possible execution path<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">In combinational logic, the output should be completely determined by the current inputs. If the RTL says that the output should change under some conditions but does not say what should happen under other conditions, the synthesizer has to preserve the previous value.<\/span><\/p><p><span style=\"font-weight: 400;\">This is why incomplete <\/span><span style=\"font-weight: 400;\">if<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">if-else<\/span><span style=\"font-weight: 400;\">, and <\/span><span style=\"font-weight: 400;\">case<\/span><span style=\"font-weight: 400;\"> statements are common sources of inferred latches. Current FPGA synthesis documentation also specifically identifies incomplete <\/span><span style=\"font-weight: 400;\">IF<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">CASE<\/span><span style=\"font-weight: 400;\"> coverage as a common cause of unintended latch generation.<\/span><\/p><p><span style=\"font-weight: 400;\">The easiest question to ask during RTL review is:<\/span><\/p><p><b>&#8220;For every possible combination of inputs, does every combinational output get a value?&#8221;<\/b><\/p><p><span style=\"font-weight: 400;\">If the answer is no, investigate for latch inference.<\/span><\/p><h3><span style=\"font-weight: 400;\">The Most Common Cause: Incomplete if Statements<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(*) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">sel<\/span><span style=\"font-weight: 400;\"> is 1:<\/span><\/p><p><span style=\"font-weight: 400;\">out = a<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">But when <\/span><span style=\"font-weight: 400;\">sel<\/span><span style=\"font-weight: 400;\"> is 0, <\/span><span style=\"font-weight: 400;\">out<\/span><span style=\"font-weight: 400;\"> is not assigned.<\/span><\/p><p><span style=\"font-weight: 400;\">The synthesizer interprets the missing assignment as:<\/span><\/p><p><span style=\"font-weight: 400;\">if sel = 1 \u2192 update out<\/span><\/p><p><span style=\"font-weight: 400;\">if sel = 0 \u2192 keep previous out<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">That &#8220;keep the previous value&#8221; behavior is storage behavior.<\/span><\/p><h4><span style=\"font-weight: 400;\">Better Approach<\/span><\/h4><p><span style=\"font-weight: 400;\">Use an explicit <\/span><span style=\"font-weight: 400;\">else<\/span><span style=\"font-weight: 400;\">:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(*) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Or use a default assignment:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(*) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0out = b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Both describe combinational behavior.<\/span><\/p><p><span style=\"font-weight: 400;\">The default-assignment approach is often easier to maintain because adding another condition later is less likely to introduce an uncovered path.<\/span><\/p><h3><span style=\"font-weight: 400;\">Nested Conditions Can Hide Latches<\/span><\/h3><p><span style=\"font-weight: 400;\">Latch problems become harder to spot when conditions are nested.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (mode) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The outer <\/span><span style=\"font-weight: 400;\">if<\/span><span style=\"font-weight: 400;\"> has an <\/span><span style=\"font-weight: 400;\">else<\/span><span style=\"font-weight: 400;\">, so the code may initially appear complete.<\/span><\/p><p><span style=\"font-weight: 400;\">But consider:<\/span><\/p><p><span style=\"font-weight: 400;\">mode = 1<\/span><\/p><p><span style=\"font-weight: 400;\">enable = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There is still no assignment to <\/span><span style=\"font-weight: 400;\">out<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore, a latch can be inferred.<\/span><\/p><p><span style=\"font-weight: 400;\">A safer coding style is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0out = 1&#8217;b0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (mode) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0out = data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The default value covers the path where <\/span><span style=\"font-weight: 400;\">mode<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">enable<\/span><span style=\"font-weight: 400;\"> do not activate the assignment.<\/span><\/p><p><span style=\"font-weight: 400;\">This is an important lesson: <\/span><b>do not judge completeness only by looking for an <\/b><b>else<\/b><b>. Trace every possible path through the logic.<\/b><\/p><h3><span style=\"font-weight: 400;\">Case Statements Are Another Major Source<\/span><\/h3><p><span style=\"font-weight: 400;\">Incomplete <\/span><span style=\"font-weight: 400;\">case<\/span><span style=\"font-weight: 400;\"> statements can also produce latches.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b00: out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: out = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b10: out = c;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">What happens when:<\/span><\/p><p><span style=\"font-weight: 400;\">sel = 2&#8217;b11<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There is no assignment to <\/span><span style=\"font-weight: 400;\">out<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">The synthesizer may therefore infer storage.<\/span><\/p><p><span style=\"font-weight: 400;\">A safer implementation is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b00: out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: out = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b10: out = c;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default: out = 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Alternatively, assign a default value before the case:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0out = 1&#8217;b0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b00: out = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: out = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b10: out = c;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The default-assignment technique is particularly useful when several outputs are controlled by the same combinational block.<\/span><\/p><h3><span style=\"font-weight: 400;\">Use always_comb for Combinational RTL<\/span><\/h3><p><span style=\"font-weight: 400;\">If the design uses SystemVerilog, <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> is generally preferable to manually maintaining sensitivity lists.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = a &amp; b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The construct explicitly communicates that the block is intended to represent combinational logic. SystemVerilog tools can also perform additional checks associated with <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\">, including identifying behavior that does not satisfy the intended combinational semantics.<\/span><\/p><p><span style=\"font-weight: 400;\">Compare that with older Verilog-style coding:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(a or b) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = a &amp; b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The manual sensitivity list becomes another potential maintenance problem if the block later starts depending on another signal.<\/span><\/p><p><span style=\"font-weight: 400;\">Using:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(*)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">is much safer than manually listing signals, but when SystemVerilog is available, <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> makes design intent clearer.<\/span><\/p><h3><span style=\"font-weight: 400;\">Default Assignments: One of the Simplest Latch Prevention Techniques<\/span><\/h3><p><span style=\"font-weight: 400;\">A very practical RTL coding habit is to assign default values at the beginning of every combinational process.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0ready\u00a0 \u00a0 \u00a0 = 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid\u00a0 \u00a0 \u00a0 = 1&#8217;b0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (condition) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = ACTIVE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0valid\u00a0 \u00a0 \u00a0 = 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The defaults establish the behavior for every path. Specific conditions then override those values.<\/span><\/p><p><span style=\"font-weight: 400;\">This style has another advantage: it makes the designer&#8217;s intent visible during code review.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of trying to mentally identify every missing branch, a reviewer can first see the baseline behavior and then examine which conditions modify it.<\/span><\/p><h3><span style=\"font-weight: 400;\">Be Careful With Multiple Outputs<\/span><\/h3><p><span style=\"font-weight: 400;\">Latch inference is not limited to a single output.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0valid = 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\"> is fully assigned, but <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is not assigned when <\/span><span style=\"font-weight: 400;\">sel<\/span><span style=\"font-weight: 400;\"> is 0.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore, <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> can require storage.<\/span><\/p><p><span style=\"font-weight: 400;\">A better implementation is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y \u00a0 \u00a0 = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid = 1&#8217;b0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y \u00a0 \u00a0 = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0valid = 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">When checking a combinational block, review <\/span><b>every left-hand-side signal independently<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">One correctly assigned output does not make the entire block latch-free.<\/span><\/p><h3><span style=\"font-weight: 400;\">Latches in FSM Next-State Logic<\/span><\/h3><p><span style=\"font-weight: 400;\">Finite-state machines are another area where accidental latches commonly appear.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (state)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0IDLE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (start)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = RUN;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0RUN: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (done)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There are multiple missing assignments.<\/span><\/p><p><span style=\"font-weight: 400;\">What should <\/span><span style=\"font-weight: 400;\">next_state<\/span><span style=\"font-weight: 400;\"> be when:<\/span><\/p><p><span style=\"font-weight: 400;\">state = IDLE<\/span><\/p><p><span style=\"font-weight: 400;\">start = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Or:<\/span><\/p><p><span style=\"font-weight: 400;\">state = RUN<\/span><\/p><p><span style=\"font-weight: 400;\">done = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The intended behavior is often to remain in the current state.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of relying on incomplete assignments to imply that behavior, make it explicit:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0next_state = state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (state)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0IDLE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (start)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = RUN;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0RUN: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (done)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is much easier to understand and review.<\/span><\/p><p><span style=\"font-weight: 400;\">The default:<\/span><\/p><p><span style=\"font-weight: 400;\">next_state = state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">clearly expresses the &#8220;stay in the current state unless a transition condition is met&#8221; behavior.<\/span><\/p><h3><span style=\"font-weight: 400;\">Do Not Confuse Latches With Flip-Flops<\/span><\/h3><p><span style=\"font-weight: 400;\">A latch and a flip-flop are both storage elements, but they are not interchangeable.<\/span><\/p><p><span style=\"font-weight: 400;\">A flip-flop is normally inferred from edge-triggered sequential RTL:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A latch is level-sensitive.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, intentional latch behavior may be described using:<\/span><\/p><p><span style=\"font-weight: 400;\">always_latch begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">SystemVerilog provides <\/span><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\">, and <\/span><span style=\"font-weight: 400;\">always_latch<\/span><span style=\"font-weight: 400;\"> to make the intended hardware model clearer to tools and other engineers.<\/span><\/p><p><span style=\"font-weight: 400;\">The goal is therefore not:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Never use latches.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">The better rule is:<\/span><\/p><p><b>Never allow a latch to appear unintentionally.<\/b><\/p><p><span style=\"font-weight: 400;\">If a latch is genuinely required, describe it explicitly and document why it exists.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why Unintended Latches Are a Problem<\/span><\/h3><p><span style=\"font-weight: 400;\">An accidental latch can create several downstream problems.<\/span><\/p><h5><span style=\"font-weight: 400;\">1. Timing becomes more complicated<\/span><\/h5><p><span style=\"font-weight: 400;\">Latch-based timing analysis is different from straightforward edge-triggered flip-flop timing. The design team must account for transparency windows and related timing relationships.<\/span><\/p><h5><span style=\"font-weight: 400;\">2. Simulation and hardware behavior can become confusing<\/span><\/h5><p><span style=\"font-weight: 400;\">An output that retains its previous value may look unexpected during RTL simulation, especially when the designer thought the block was purely combinational.<\/span><\/p><h5><span style=\"font-weight: 400;\">3. Debugging becomes harder<\/span><\/h5><p><span style=\"font-weight: 400;\">A latch introduces state into a block that may have been intended to be stateless.<\/span><\/p><p><span style=\"font-weight: 400;\">That can make waveforms difficult to interpret because an output is no longer determined solely by the current input values.<\/span><\/p><h5><span style=\"font-weight: 400;\">4. Physical implementation can become more complicated<\/span><\/h5><p><span style=\"font-weight: 400;\">Unintended storage elements affect synthesis, timing, area, power, and downstream implementation decisions.<\/span><\/p><h5><span style=\"font-weight: 400;\">5. It can indicate a deeper RTL specification problem<\/span><\/h5><p><span style=\"font-weight: 400;\">A latch warning is sometimes more than a coding issue. It can reveal that the specification itself does not clearly define what the output should do under certain conditions.<\/span><\/p><h3><span style=\"font-weight: 400;\">Use Lint and Synthesis Reports<\/span><\/h3><p><span style=\"font-weight: 400;\">Good RTL development should not depend entirely on manual inspection.<\/span><\/p><p><span style=\"font-weight: 400;\">RTL lint tools can identify incomplete assignments and other coding problems before the design reaches synthesis. Synthesis tools also report inferred storage elements, and those warnings should be investigated rather than ignored.<\/span><\/p><p><span style=\"font-weight: 400;\">A practical development cycle is:<\/span><\/p><p><span style=\"font-weight: 400;\">Write RTL<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Run simulation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Run RTL lint<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Review latch warnings<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Run synthesis<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Review inferred hardware<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Fix unintended storage<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If a combinational block unexpectedly produces a latch in the synthesis report, go back to the RTL and identify which signal lacks a complete assignment path.<\/span><\/p><h3><span style=\"font-weight: 400;\">A Practical Latch-Prevention Checklist<\/span><\/h3><p><span style=\"font-weight: 400;\">Before committing a combinational RTL block, ask:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does every output receive a value on every possible path?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does every <\/span><span style=\"font-weight: 400;\">if<\/span><span style=\"font-weight: 400;\"> statement have an intentional <\/span><span style=\"font-weight: 400;\">else<\/span><span style=\"font-weight: 400;\"> or a safe default assignment?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does every <\/span><span style=\"font-weight: 400;\">case<\/span><span style=\"font-weight: 400;\"> statement handle uncovered conditions appropriately?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are default assignments placed at the beginning of complex combinational blocks?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Is <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> being used where SystemVerilog is available?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are FSM next-state signals assigned sensible defaults?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are all outputs checked individually?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are latch warnings from lint being reviewed?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are synthesis reports showing any unexpected latch cells?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">If a latch is intentional, is it explicitly coded and documented?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This checklist catches a large percentage of accidental latch problems before they become more expensive to debug.<\/span><\/p><h4><span style=\"font-weight: 400;\">Final Thoughts<\/span><\/h4><p><span style=\"font-weight: 400;\">Inferred latches are rarely caused by complicated hardware concepts. More often, they come from a small gap between what the designer intended and what the RTL actually specified.<\/span><\/p><p><span style=\"font-weight: 400;\">An incomplete <\/span><span style=\"font-weight: 400;\">if<\/span><span style=\"font-weight: 400;\">, a missing <\/span><span style=\"font-weight: 400;\">default<\/span><span style=\"font-weight: 400;\"> in a <\/span><span style=\"font-weight: 400;\">case<\/span><span style=\"font-weight: 400;\">, or an overlooked output assignment can be enough to turn apparently simple combinational logic into storage.<\/span><\/p><p><span style=\"font-weight: 400;\">The most reliable approach is to make combinational behavior explicit. Use complete assignments, establish sensible defaults, write FSM next-state logic carefully, prefer <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> for SystemVerilog combinational logic, and treat lint and synthesis warnings as part of the design process rather than as optional cleanup.<\/span><\/p><p><span style=\"font-weight: 400;\">Most importantly, remember the core rule:<\/span><\/p><p><span style=\"font-weight: 400;\">If a combinational output must never remember its previous value, make sure the RTL assigns it a value for every possible path.<\/span><\/p><p><span style=\"font-weight: 400;\">That simple discipline can prevent many RTL bugs and help produce cleaner, more predictable synthesis results.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Writing RTL that synthesizes into the hardware you actually intended is one of the most important skills for a digital design engineer. A few lines of incomplete Verilog can be enough to create hardware that was never part of the original design plan. One common example is unintended latch inference. Latches are not inherently bad. [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10102","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>How to Avoid Inferred Latches in RTL Design | RTL Coding Guide<\/title>\n<meta name=\"description\" content=\"Learn how to avoid inferred latches in RTL design using complete assignments, always_comb, proper if-else and case coding, and effective lint and synthesis checks.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/inskill.in\/training\/https-inskill-in-online\/\" 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