{"id":10145,"date":"2026-09-07T10:18:22","date_gmt":"2026-09-07T10:18:22","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10145"},"modified":"2026-09-15T10:20:06","modified_gmt":"2026-09-15T10:20:06","slug":"ready-valid-handshake-protocol-rtl","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/ready-valid-handshake-protocol-rtl\/","title":{"rendered":"Ready-Valid Handshake Protocol Explained for RTL Engineers"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10145\" class=\"elementor elementor-10145\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-fd4176b elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"fd4176b\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-d28f0b5\" data-id=\"d28f0b5\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-4abf2fa elementor-widget elementor-widget-text-editor\" data-id=\"4abf2fa\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">When two RTL modules need to exchange data, simply connecting a data bus between them is not enough. The receiving module may not always be ready to accept data, while the transmitting module may have new data available at a different time.<\/span><\/p><p><span style=\"font-weight: 400;\">The ready-valid handshake protocol solves this problem with two control signals: <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">The source uses <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> to indicate that it has valid data available, while the destination uses <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> to indicate that it can accept the data. A data transfer takes place on a clock edge when both signals are high. This simple mechanism is widely used in RTL pipelines, streaming interfaces, and protocols such as AXI4-Stream.<\/span><\/p><p><span style=\"font-weight: 400;\">For RTL engineers, understanding the ready-valid handshake is important because incorrect handling of these signals can result in dropped data, duplicated transactions, pipeline stalls, or even deadlock.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a Ready-Valid Handshake?<\/span><\/h3><p><span style=\"font-weight: 400;\">A ready-valid interface normally consists of:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> \u2013 asserted by the source when valid data is available<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> \u2013 asserted by the destination when it can accept data<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">data<\/span><span style=\"font-weight: 400;\"> \u2013 the information being transferred<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">clk<\/span><span style=\"font-weight: 400;\"> \u2013 the common clock used by the interface<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A transfer occurs when:<\/span><\/p><p><span style=\"font-weight: 400;\">valid = 1<\/span><\/p><p><span style=\"font-weight: 400;\">ready = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">at the active clock edge.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Ready-Valid Interface<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Source \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Destination<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|&#8212;&#8212; data &#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&gt;|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|&#8212;&#8212; valid &#8212;&#8212;&#8212;&#8212;&#8212;&#8211;&gt;|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|&lt;&#8212;&#8211; ready &#8212;&#8212;&#8212;&#8212;&#8212;&#8212;|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;- Transfer when both = 1 &#8212;+<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The important point is that neither <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> nor <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> alone means that a transfer has occurred.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><table><tbody><tr><td><p><b>VALID<\/b><\/p><\/td><td><p><b>READY<\/b><\/p><\/td><td><p><b>Transfer<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">0<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">0<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">No<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">0<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">1<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">No<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">1<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">0<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">No<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">1<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">1<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">This behavior is also reflected in current AMD documentation for ready\/valid interfaces, where a valid transfer occurs when both <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> are high at the relevant rising clock edge.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">How the Ready-Valid Handshake Works<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider a producer that has a 32-bit data word to send.<\/span><\/p><p><span style=\"font-weight: 400;\">The producer asserts:<\/span><\/p><p><span style=\"font-weight: 400;\">valid = 1<\/span><\/p><p><span style=\"font-weight: 400;\">data\u00a0 = 32&#8217;h12345678<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The consumer is currently busy, so it keeps:<\/span><\/p><p><span style=\"font-weight: 400;\">ready = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">No transfer occurs.<\/span><\/p><p><span style=\"font-weight: 400;\">The producer must keep <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> asserted and maintain the corresponding data until the destination becomes ready.<\/span><\/p><p><span style=\"font-weight: 400;\">When the consumer eventually asserts:<\/span><\/p><p><span style=\"font-weight: 400;\">ready = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the next active clock edge completes the transfer.<\/span><\/p><p><span style=\"font-weight: 400;\">Cycle \u00a0 \u00a0 \u00a0 VALID \u00a0 \u00a0 \u00a0 READY \u00a0 \u00a0 \u00a0 Transfer<\/span><\/p><p><span style=\"font-weight: 400;\">&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;<\/span><\/p><p><span style=\"font-weight: 400;\">1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 No<\/span><\/p><p><span style=\"font-weight: 400;\">2 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 No<\/span><\/p><p><span style=\"font-weight: 400;\">3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Yes<\/span><\/p><p><span style=\"font-weight: 400;\">4 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 No<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is the basic mechanism behind ready-valid flow control.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">What Does VALID Mean?<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> signal is controlled by the <\/span><b>source<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is high, the source is saying:<\/span><\/p><p><span style=\"font-weight: 400;\">\u201cI have a valid transaction available on the data bus.\u201d<\/span><\/p><p><span style=\"font-weight: 400;\">The source should not assert <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> merely because it expects the destination to be ready.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead, <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> should indicate that the source actually has a transaction to send.<\/span><\/p><p><span style=\"font-weight: 400;\">One of the most important rules is:<\/span><\/p><p><b>The source must not wait for <\/b><b>ready<\/b><b> before asserting <\/b><b>valid<\/b><b>.<\/b><\/p><p><span style=\"font-weight: 400;\">If both sides wait for the other to act first, the interface can deadlock. SystemVerilog.dev specifically identifies this as a common ready-valid design pitfall.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">What Does READY Mean?<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> signal is controlled by the <\/span><b>destination<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> is high, the destination is indicating:<\/span><\/p><p><span style=\"font-weight: 400;\">\u201cI can accept a transaction.\u201d<\/span><\/p><p><span style=\"font-weight: 400;\">The destination may assert <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> before <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> arrives.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">does not transfer anything.<\/span><\/p><p><span style=\"font-weight: 400;\">But if the source subsequently asserts <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\">:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the transfer can occur on the next active clock edge.<\/span><\/p><p><span style=\"font-weight: 400;\">This ability for either side to independently indicate its state makes the ready-valid protocol useful for modular RTL design.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">The Most Important Ready-Valid Rule<\/span><\/h3><p><span style=\"font-weight: 400;\">Suppose the source asserts:<\/span><\/p><p><span style=\"font-weight: 400;\">valid = 1<\/span><\/p><p><span style=\"font-weight: 400;\">data\u00a0 = A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">but the destination has:<\/span><\/p><p><span style=\"font-weight: 400;\">ready = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The source must hold the transaction.<\/span><\/p><p><span style=\"font-weight: 400;\">It should not change the data to <\/span><span style=\"font-weight: 400;\">B<\/span><span style=\"font-weight: 400;\"> simply because the destination has not accepted <\/span><span style=\"font-weight: 400;\">A<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">Cycle \u00a0 \u00a0 \u00a0 VALID \u00a0 \u00a0 \u00a0 READY \u00a0 \u00a0 \u00a0 DATA<\/span><\/p><p><span style=\"font-weight: 400;\">&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;<\/span><\/p><p><span style=\"font-weight: 400;\">1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 A<\/span><\/p><p><span style=\"font-weight: 400;\">2 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 A<\/span><\/p><p><span style=\"font-weight: 400;\">3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 0\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 A<\/span><\/p><p><span style=\"font-weight: 400;\">4 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 1\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The transfer occurs in Cycle 4.<\/span><\/p><p><span style=\"font-weight: 400;\">After that transfer, the source can present the next transaction.<\/span><\/p><p><span style=\"font-weight: 400;\">This rule prevents the receiver from sampling inconsistent or changing data.<\/span><\/p><p><span style=\"font-weight: 400;\">For AXI-style interfaces, the same principle applies: once <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> is asserted, the associated transfer information must remain stable until the handshake completes.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Ready-Valid Handshake Timing<\/span><\/h3><p><span style=\"font-weight: 400;\">A simple timing sequence can be represented as:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| 1 | 2 | 3 | 4 | 5 |<\/span><\/p><p><span style=\"font-weight: 400;\">CLK \u00a0 \u00a0 |\u2191\u00a0 |\u2191\u00a0 |\u2191\u00a0 |\u2191\u00a0 |\u2191\u00a0 |<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">VALID \u00a0 | 0 | 1 | 1 | 1 | 0 |<\/span><\/p><p><span style=\"font-weight: 400;\">READY \u00a0 | 0 | 0 | 1 | 1 | 1 |<\/span><\/p><p><span style=\"font-weight: 400;\">DATA\u00a0 \u00a0 | &#8211; | A | A | B | &#8211; |<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0^<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Transfer A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">At Cycle 3:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Therefore, data <\/span><span style=\"font-weight: 400;\">A<\/span><span style=\"font-weight: 400;\"> is transferred.<\/span><\/p><p><span style=\"font-weight: 400;\">If the source has another transaction immediately available, it can keep <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> high and place the next data item on the bus.<\/span><\/p><p><span style=\"font-weight: 400;\">This allows <\/span><b>one transfer per clock cycle<\/b><span style=\"font-weight: 400;\"> when both sides remain ready.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Ready-Valid Handshake and Backpressure<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the biggest advantages of the ready-valid protocol is <\/span><b>backpressure<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Backpressure occurs when a downstream module temporarily cannot accept more data.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Module A \u2192 Module B \u2192 Module C<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If Module C becomes busy, Module B may eventually stop accepting data from Module A.<\/span><\/p><p><span style=\"font-weight: 400;\">The <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> signal propagates this condition backward.<\/span><\/p><p><span style=\"font-weight: 400;\">Module A<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Module B<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Module C<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0X Busy<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Module C can deassert <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Module B then stops accepting additional data when its available buffering is exhausted.<\/span><\/p><p><span style=\"font-weight: 400;\">This prevents uncontrolled data flow and helps connect pipelines with different processing rates.<\/span><\/p><p><span style=\"font-weight: 400;\">Ready-valid interfaces are therefore particularly useful in streaming and pipelined RTL architectures.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Ready-Valid Handshake in RTL<\/span><\/h3><p><span style=\"font-weight: 400;\">A simple SystemVerilog interface might look like this:<\/span><\/p><p><span style=\"font-weight: 400;\">module data_source #(<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0parameter int WIDTH = 32<\/span><\/p><p><span style=\"font-weight: 400;\">)(<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 clk,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 rst_n,<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 valid,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic [WIDTH-1:0] data,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 ready<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0always_ff @(posedge clk or negedge rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (!rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0valid &lt;= 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0data\u00a0 &lt;= &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0else begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (!valid || ready) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0valid &lt;= 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0data\u00a0 &lt;= next_data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endmodule<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact implementation depends on the behavior of the source, but the important principle is that the source retains the transaction while <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is high and <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> is low.<\/span><\/p><p><span style=\"font-weight: 400;\">The transfer condition can be expressed as:<\/span><\/p><p><span style=\"font-weight: 400;\">assign transfer = valid &amp;&amp; ready;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">At every active clock edge where this condition is true, one transaction is accepted.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Why VALID Must Not Wait for READY<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider this incorrect behavior:<\/span><\/p><p><span style=\"font-weight: 400;\">Source:<\/span><\/p><p><span style=\"font-weight: 400;\">if (ready)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid = 1;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><span style=\"font-weight: 400;\">Destination:<\/span><\/p><p><span style=\"font-weight: 400;\">if (valid)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0ready = 1;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Now both modules can wait indefinitely.<\/span><\/p><p><span style=\"font-weight: 400;\">The source waits for <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">The destination waits for <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Neither signal becomes active.<\/span><\/p><p><span style=\"font-weight: 400;\">This is a classic deadlock scenario.<\/span><\/p><p><span style=\"font-weight: 400;\">A safer design is:<\/span><\/p><p><span style=\"font-weight: 400;\">Source:<\/span><\/p><p><span style=\"font-weight: 400;\">valid depends on whether data is available<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Destination:<\/span><\/p><p><span style=\"font-weight: 400;\">ready depends on whether it can accept data<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The two signals should be generated independently enough that the interface can make progress.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Avoid Combinational Loops<\/span><\/h3><p><span style=\"font-weight: 400;\">Another important RTL design issue occurs when <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> are connected through combinational dependencies.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Source VALID\u00a0 &#8212;&gt; Destination READY<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0^\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|____________________|<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If the source calculates <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> directly from <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\">, while the destination calculates <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> directly from <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\">, the design can create a combinational loop.<\/span><\/p><p><span style=\"font-weight: 400;\">This can lead to:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Timing problems<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unpredictable simulation behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Difficult synthesis<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Poor scalability<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Potential deadlock<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">SystemVerilog.dev recommends avoiding such combinational loops in ready-valid interfaces and using registered signals or state-based logic where appropriate.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Ready-Valid Handshake vs Request-Acknowledge<\/span><\/h3><p><span style=\"font-weight: 400;\">Ready-valid and request-acknowledge handshakes are related but should not be treated as identical protocols.<\/span><\/p><table><tbody><tr><td><p><b>Feature<\/b><\/p><\/td><td><p><b>Ready-Valid<\/b><\/p><\/td><td><p><b>Request-Acknowledge<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Main signals<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">ready<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">req<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">ack<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Typical use<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Streaming data<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Control\/event transfer<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Data transfer<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">valid &amp;&amp; ready<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Depends on protocol<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Backpressure<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Naturally supported<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Can be implemented<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Common application<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">RTL pipelines, AXI streams<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Control interfaces<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">Ready-valid is especially effective when a design needs continuous data movement and flow control.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Ready-Valid Handshake and AXI<\/span><\/h3><p><span style=\"font-weight: 400;\">The ready-valid mechanism is strongly associated with <\/span><b>AMBA AXI<\/b><span style=\"font-weight: 400;\">, particularly AXI4-Stream.<\/span><\/p><p><span style=\"font-weight: 400;\">However, ready-valid is not limited to AXI.<\/span><\/p><p><span style=\"font-weight: 400;\">It is a general RTL interface pattern that can be used whenever one synchronous module needs to transfer transactions to another while allowing the destination to control the flow rate.<\/span><\/p><p><span style=\"font-weight: 400;\">AXI4-Stream uses the same fundamental idea: a transfer occurs when <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> are asserted at the appropriate clock edge.<\/span><\/p><p><span style=\"font-weight: 400;\">This is why understanding ready-valid signaling is useful before learning more complex AXI interfaces.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Common Ready-Valid Handshake Mistakes<\/span><\/h3><h4><span style=\"font-weight: 400;\">1. Deasserting VALID before the transfer<\/span><\/h4><p><span style=\"font-weight: 400;\">If:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the source should not withdraw the transaction.<\/span><\/p><p><span style=\"font-weight: 400;\">It should keep the transaction available until the destination accepts it.<\/span><\/p><h4><span style=\"font-weight: 400;\">2. Changing DATA while VALID is waiting<\/span><\/h4><p><span style=\"font-weight: 400;\">Changing data while <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> remains asserted and <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> is low can cause the receiver to observe the wrong transaction.<\/span><\/p><h4><span style=\"font-weight: 400;\">3. Making VALID depend directly on READY<\/span><\/h4><p><span style=\"font-weight: 400;\">This can introduce deadlock.<\/span><\/p><h4><span style=\"font-weight: 400;\">4. Creating a combinational READY-VALID loop<\/span><\/h4><p><span style=\"font-weight: 400;\">This can create problematic timing paths between connected modules.<\/span><\/p><h4><span style=\"font-weight: 400;\">5. Assuming VALID alone means transfer<\/span><\/h4><p><span style=\"font-weight: 400;\">It does not.<\/span><\/p><p><span style=\"font-weight: 400;\">The transfer condition is:<\/span><\/p><p><span style=\"font-weight: 400;\">valid &amp;&amp; ready<\/span><\/p><p>\u00a0<\/p><h4><span style=\"font-weight: 400;\">6. Ignoring backpressure<\/span><\/h4><p><span style=\"font-weight: 400;\">A downstream module may temporarily stop accepting data. The upstream logic must handle this condition correctly rather than continuously overwriting or discarding transactions.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">How to Verify a Ready-Valid Interface<\/span><\/h3><p><span style=\"font-weight: 400;\">Ready-valid interfaces should be verified for both normal transfers and stalled conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">Important scenarios include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID=0<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">READY=0<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID=0<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">READY=1<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID=1<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">READY=0<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID=1<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">READY=1<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiple consecutive transfers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Destination stalls for several cycles<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Source stalls before producing data<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset during idle operation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset followed by immediate traffic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Back-to-back transactions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A useful SystemVerilog assertion is to check that data remains stable when a transaction is waiting:<\/span><\/p><p><span style=\"font-weight: 400;\">property valid_data_stable;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready |=&gt; valid &amp;&amp; $stable(data);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (valid_data_stable);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Inskill&#8217;s existing material on assertion-based verification also demonstrates checking valid-ready behavior using SystemVerilog Assertions, so this topic naturally connects to verification-oriented RTL learning.<\/span><\/p><p>\u00a0<\/p><h4><span style=\"font-weight: 400;\">Ready-Valid Handshake: Key Takeaways<\/span><\/h4><p><span style=\"font-weight: 400;\">The ready-valid handshake protocol is one of the most useful interface patterns for RTL engineers.<\/span><\/p><p><span style=\"font-weight: 400;\">The concept is simple:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = Source has a transaction<\/span><\/p><p><span style=\"font-weight: 400;\">READY = Destination can accept it<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Transfer = VALID &amp;&amp; READY<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">But the implementation details matter.<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is high and <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> is low, the source must continue presenting the same transaction. The source should not wait for <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> before making <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> active, because doing so can create deadlock. Designers should also avoid inappropriate combinational dependencies between <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Once these rules are understood, ready-valid interfaces become much easier to apply to RTL pipelines, streaming data paths, AXI interfaces, DMA engines, FIFOs, and other SoC communication structures.<\/span><\/p><p><span style=\"font-weight: 400;\">For an RTL engineer, mastering this protocol is less about memorizing two signals and more about understanding data stability, flow control, backpressure, throughput, and safe module-to-module communication.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>When two RTL modules need to exchange data, simply connecting a data bus between them is not enough. The receiving module may not always be ready to accept data, while the transmitting module may have new data available at a different time. The ready-valid handshake protocol solves this problem with two control signals: valid and [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10145","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Ready-Valid Handshake Protocol: RTL Guide<\/title>\n<meta name=\"description\" content=\"Learn the ready-valid handshake protocol for RTL design, including VALID, READY, data transfer, backpressure, AXI, SystemVerilog and common RTL mistakes.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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