{"id":10170,"date":"2026-09-14T11:01:00","date_gmt":"2026-09-14T11:01:00","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10170"},"modified":"2026-09-15T11:09:40","modified_gmt":"2026-09-15T11:09:40","slug":"low-power-verification-with-upf","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/low-power-verification-with-upf\/","title":{"rendered":"Low-Power Verification with UPF: A Beginner&#8217;s Introduction"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10170\" class=\"elementor elementor-10170\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e46457c elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e46457c\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-b3a4d88\" data-id=\"b3a4d88\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-2f5afc5 elementor-widget elementor-widget-text-editor\" data-id=\"2f5afc5\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">Modern SoCs rarely operate with a single power supply or a single operating mode. Different blocks may run at different voltages, some blocks may be switched off when they are not required, and important register states may need to be preserved during power-down.<\/span><\/p><p><span style=\"font-weight: 400;\">These techniques help reduce power consumption, but they also introduce new verification problems. A design that works correctly when every block is powered on may fail when a domain is switched off, restored, or operated at a different voltage.<\/span><\/p><p><span style=\"font-weight: 400;\">This is where low-power verification with UPF becomes important.<\/span><\/p><p><span style=\"font-weight: 400;\">The Unified Power Format (UPF), standardized as IEEE 1801, provides a way to describe the power intent of a design separately from its functional RTL. The power intent can then be used across design, verification and implementation flows.<\/span><\/p><p><span style=\"font-weight: 400;\">For beginners, the important point is simple:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL describes what the design does. UPF describes how the design is powered and what should happen when power conditions change<\/span><b>.<\/b><\/p><p><span style=\"font-weight: 400;\">This guide explains the fundamentals of UPF-based low-power verification and the concepts a beginner should understand before working on real SoC designs.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Low-Power Verification?<\/span><\/h3><p><span style=\"font-weight: 400;\">Traditional functional verification primarily checks whether the RTL behaves according to its specification.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a verification environment may check whether:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A FIFO correctly handles read and write operations<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An AXI interface follows the protocol<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A processor produces the expected result<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A register receives the correct value<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An FSM transitions between states correctly<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Low-power verification adds another dimension.<\/span><\/p><p><span style=\"font-weight: 400;\">The verification environment must also determine whether the design behaves correctly when:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A power domain is switched off<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A power domain is switched back on<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Two domains operate at different voltages<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Signals cross between power domains<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Register state needs to be retained<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Isolation needs to be enabled<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Different power states are entered<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power-management controls change in a particular sequence<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Therefore, a low-power design can be functionally correct and still have a power-intent bug.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, imagine that a CPU subsystem is powered down while another always-on subsystem continues operating. If signals from the powered-down block are allowed to reach the active block without proper isolation, the receiving logic may see invalid values.<\/span><\/p><p><span style=\"font-weight: 400;\">Low-power verification is intended to detect such problems before implementation or silicon.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is UPF?<\/span><\/h3><p><b>UPF stands for Unified Power Format.<\/b><\/p><p><span style=\"font-weight: 400;\">It is used to describe the power intent of a design. IEEE 1801 defines the standard for specifying and working with power intent in energy-aware electronic systems.<\/span><\/p><p><span style=\"font-weight: 400;\">The functional RTL might describe a block such as:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU \u2192 Memory Controller \u2192 Peripheral<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The UPF description can additionally define:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU Domain \u00a0 \u00a0 \u00a0 \u2192 Switchable<\/span><\/p><p><span style=\"font-weight: 400;\">Memory Domain\u00a0 \u00a0 \u2192 Always ON<\/span><\/p><p><span style=\"font-weight: 400;\">Peripheral \u00a0 \u00a0 \u00a0 \u2192 Different Voltage<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">It can also describe requirements such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which blocks belong to each power domain<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which supply powers a domain<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">When a domain can be switched off<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which signals require isolation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which signals require voltage level shifting<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which registers need state retention<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What power states are legal<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">UPF therefore complements RTL rather than replacing it.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why Is UPF Needed for Low-Power Verification?<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider a simple SoC with two power domains:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 Always-On\u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 Domain \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8211;+&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Isolation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8211;v&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 Switchable \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 Domain \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The switchable domain can be powered down to save leakage power.<\/span><\/p><p><span style=\"font-weight: 400;\">When it is ON, it behaves normally.<\/span><\/p><p><span style=\"font-weight: 400;\">When it is OFF, however, its outputs cannot simply be treated like normal functional signals.<\/span><\/p><p><span style=\"font-weight: 400;\">The verification environment needs to check:<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Was the domain switched off at the correct time?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Was isolation enabled before the shutdown?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Were outputs clamped to the expected value?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Was required state saved?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Was the state restored correctly?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Was the domain powered on in the correct sequence?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Did the design return to functional operation after wake-up?<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">These are examples of problems that traditional RTL-only simulation may not adequately represent.<\/span><\/p><h3><span style=\"font-weight: 400;\">Important UPF Concepts Beginners Should Know<\/span><\/h3><p><span style=\"font-weight: 400;\">Before learning UPF commands, beginners should understand several basic low-power concepts.<\/span><\/p><h5><span style=\"font-weight: 400;\">1. Power Domains<\/span><\/h5><p><span style=\"font-weight: 400;\">A <\/span><b>power domain<\/b><span style=\"font-weight: 400;\"> is a logical group of design elements that share a particular power supply arrangement.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">PD_TOP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u251c\u2500\u2500 CPU<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u251c\u2500\u2500 Cache<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2514\u2500\u2500 Control Logic<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">PD_PERIPH<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u251c\u2500\u2500 UART<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u251c\u2500\u2500 SPI<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2514\u2500\u2500 GPIO<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The domains may have different power characteristics.<\/span><\/p><p><span style=\"font-weight: 400;\">One domain may remain powered continuously while another can be switched off.<\/span><\/p><p><span style=\"font-weight: 400;\">In UPF, power domains are part of the power-intent description.<\/span><\/p><h5><span style=\"font-weight: 400;\">2. Power Supply Network<\/span><\/h5><p><span style=\"font-weight: 400;\">A low-power design may have multiple supply rails.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">VDD_AON<\/span><\/p><p><span style=\"font-weight: 400;\">VDD_CPU<\/span><\/p><p><span style=\"font-weight: 400;\">VDD_PERIPH<\/span><\/p><p><span style=\"font-weight: 400;\">VSS<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The UPF power intent describes the supply architecture and its relationship with power domains.<\/span><\/p><p><span style=\"font-weight: 400;\">This becomes important when different blocks operate at different voltages or when a domain can be disconnected from its supply.<\/span><\/p><h5><span style=\"font-weight: 400;\">3. Isolation Cells<\/span><\/h5><p><span style=\"font-weight: 400;\">Isolation is one of the most important concepts in low-power verification.<\/span><\/p><p><span style=\"font-weight: 400;\">Suppose Domain A can be switched off while Domain B remains active:<\/span><\/p><p><span style=\"font-weight: 400;\">Domain A\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Domain B<\/span><\/p><p><span style=\"font-weight: 400;\">Power OFF \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Power ON<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|\u00a0 X \/ invalid<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0[Isolation]<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0Logic<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">When Domain A is powered down, its outputs may no longer contain valid logic values.<\/span><\/p><p><span style=\"font-weight: 400;\">An isolation cell prevents those invalid values from reaching active logic. It can clamp the output to a defined value such as <\/span><span style=\"font-weight: 400;\">0<\/span><span style=\"font-weight: 400;\"> or <\/span><span style=\"font-weight: 400;\">1<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Verification therefore needs to check both the <\/span><b>isolation strategy<\/b><span style=\"font-weight: 400;\"> and the <\/span><b>timing\/control of isolation<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Power Down:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0Stop activity<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0Enable isolation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0Switch domain OFF<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">During wake-up, the sequence needs to be handled correctly as well.<\/span><\/p><p><span style=\"font-weight: 400;\">Isolation verification is particularly important because the clamp value and isolation control are part of the interaction between functional behavior and power intent.<\/span><\/p><h5><span style=\"font-weight: 400;\">4. Level Shifters<\/span><\/h5><p><span style=\"font-weight: 400;\">Different power domains may operate at different voltage levels.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU Domain \u00a0 \u00a0 \u00a0 : 0.8 V<\/span><\/p><p><span style=\"font-weight: 400;\">Always-On Domain : 1.0 V<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A signal crossing between these domains may require a <\/span><b>level shifter<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">0.8 V Domain<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0| signal<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">[Level Shifter]<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">1.0 V Domain<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact implementation depends on the technology and direction of the voltage crossing.<\/span><\/p><p><span style=\"font-weight: 400;\">During low-power verification, engineers need to ensure that the intended crossings are correctly handled.<\/span><\/p><h5><span style=\"font-weight: 400;\">5. Retention<\/span><\/h5><p><span style=\"font-weight: 400;\">Powering down a domain normally means that the state stored in ordinary registers can be lost.<\/span><\/p><p><span style=\"font-weight: 400;\">But some registers may contain important information that must survive power-down.<\/span><\/p><p><span style=\"font-weight: 400;\">A retention strategy is used for such state.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified sequence is:<\/span><\/p><p><span style=\"font-weight: 400;\">Before power-down:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0SAVE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Register state preserved<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Power OFF<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Power ON<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0RESTORE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Original state recovered<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Verification must check that the correct state is saved and restored and that the state becomes valid at the expected point in the wake-up sequence.<\/span><\/p><h5><span style=\"font-weight: 400;\">6. Power States<\/span><\/h5><p><span style=\"font-weight: 400;\">A complex SoC can operate in several power states.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><table><tbody><tr><td><p><b>Power State<\/b><\/p><\/td><td><p><b>CPU<\/b><\/p><\/td><td><p><b>Peripheral<\/b><\/p><\/td><td><p><b>Description<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">ACTIVE<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">ON<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">ON<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Normal operation<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">CPU_SLEEP<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">OFF<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">ON<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">CPU powered down<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">LOW_POWER<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">LOW V<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">ON<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Reduced-voltage operation<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">DEEP_SLEEP<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">OFF<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">OFF\/limited<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Maximum power saving<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">The allowed combinations can be represented through a Power State Table (PST).<\/span><\/p><p><span style=\"font-weight: 400;\">A PST is important because verification needs to know which combinations are legal and what behavior is expected in each state. Accellera&#8217;s UPF material describes the power state table as the set of legal combinations of power-domain states.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">How Does UPF-Based Verification Work?<\/span><\/h3><p><span style=\"font-weight: 400;\">A simplified low-power verification flow can be understood in the following steps.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Create the RTL<\/span><\/h5><p><span style=\"font-weight: 400;\">The design is first described using Verilog or SystemVerilog.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, the design may contain:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">CPU logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory controller<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">UART<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DMA<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Peripheral blocks<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 2: Define the Power Architecture<\/span><\/h5><p><span style=\"font-weight: 400;\">The designer identifies:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power domains<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Supply rails<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Switchable blocks<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Always-on blocks<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Voltage differences<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Retention requirements<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Isolation requirements<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 3: Create the UPF<\/span><\/h5><p><span style=\"font-weight: 400;\">The power intent is captured using UPF.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified example might look conceptually like:<\/span><\/p><p><span style=\"font-weight: 400;\">create_power_domain PD_CPU<\/span><\/p><p><span style=\"font-weight: 400;\">create_power_domain PD_AON<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\"># Power intent definitions<\/span><\/p><p><span style=\"font-weight: 400;\"># Isolation strategy<\/span><\/p><p><span style=\"font-weight: 400;\"># Retention strategy<\/span><\/p><p><span style=\"font-weight: 400;\"># Supply definitions<\/span><\/p><p><span style=\"font-weight: 400;\"># Power states<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact UPF syntax and supported commands depend on the UPF version and EDA tool flow, so beginners should learn the concepts before memorizing commands.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 4: Run Power-Aware Simulation<\/span><\/h5><p><span style=\"font-weight: 400;\">The RTL and UPF are loaded into a power-aware simulation environment.<\/span><\/p><p><span style=\"font-weight: 400;\">The simulator can then model the effect of the defined power conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of checking only:<\/span><\/p><p><span style=\"font-weight: 400;\">Input \u2192 RTL \u2192 Output<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the verification environment can check:<\/span><\/p><p><span style=\"font-weight: 400;\">Input<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">RTL + Power Intent<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Power State Transition<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Output<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 5: Verify Power Scenarios<\/span><\/h5><p><span style=\"font-weight: 400;\">The testbench should exercise different operating conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">ACTIVE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">SAVE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">ISOLATE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">POWER DOWN<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">POWER UP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">RESTORE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">ACTIVE<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The purpose is to determine whether the design behaves correctly throughout the complete transition.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Should Be Verified in a UPF Environment?<\/span><\/h3><p><span style=\"font-weight: 400;\">A beginner should focus on these verification goals.<\/span><\/p><h5><span style=\"font-weight: 400;\">Power-domain behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Check that each domain enters and leaves its intended power states.<\/span><\/p><h5><span style=\"font-weight: 400;\">Isolation behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Check that signals are properly clamped when a source domain is powered down.<\/span><\/p><h5><span style=\"font-weight: 400;\">Retention behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Check that required register values survive power-down and are restored correctly.<\/span><\/p><h5><span style=\"font-weight: 400;\">Level-shifter behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Check that voltage-domain crossings are correctly handled.<\/span><\/p><h5><span style=\"font-weight: 400;\">Power-state transitions<\/span><\/h5><p><span style=\"font-weight: 400;\">Check legal transitions between operating modes.<\/span><\/p><h5><span style=\"font-weight: 400;\">Wake-up behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Power-up is just as important as power-down.<\/span><\/p><p><span style=\"font-weight: 400;\">The design should return to a valid functional state after restoration.<\/span><\/p><h5><span style=\"font-weight: 400;\">Control sequencing<\/span><\/h5><p><span style=\"font-weight: 400;\">The order of events matters.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, switching power off before enabling isolation could expose active logic to invalid signals.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore, verification should test not only whether controls eventually reach the correct values, but also whether they occur in the required sequence.<\/span><\/p><h3><span style=\"font-weight: 400;\">A Simple Example of UPF Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider a CPU block that can be powered down.<\/span><\/p><p><span style=\"font-weight: 400;\">During normal operation:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU = ON<\/span><\/p><p><span style=\"font-weight: 400;\">Isolation = OFF<\/span><\/p><p><span style=\"font-weight: 400;\">Retention = ACTIVE<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Before shutdown:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU activity stops<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">State is saved<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Isolation enabled<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">CPU power OFF<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">During shutdown:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU = OFF<\/span><\/p><p><span style=\"font-weight: 400;\">Isolation = ON<\/span><\/p><p><span style=\"font-weight: 400;\">State = Retained<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">During wake-up:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU power ON<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Wait for power stabilization<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Restore state<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Release isolation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">CPU resumes operation<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A power-aware test should verify each stage rather than simply checking whether the CPU eventually becomes operational.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Should a Beginner Learn Before UPF?<\/span><\/h3><p><span style=\"font-weight: 400;\">UPF is easier to learn if the fundamentals are already clear.<\/span><\/p><p><span style=\"font-weight: 400;\">A good learning sequence is:<\/span><\/p><h5><span style=\"font-weight: 400;\">1. Digital Design<\/span><\/h5><p><span style=\"font-weight: 400;\">Understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Combinational logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Sequential logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flip-flops<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSMs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Registers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock and reset<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">2. Verilog\/SystemVerilog<\/span><\/h5><p><span style=\"font-weight: 400;\">Be comfortable reading and writing RTL.<\/span><\/p><h5><span style=\"font-weight: 400;\">3. Functional Verification<\/span><\/h5><p><span style=\"font-weight: 400;\">Understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Testbenches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Simulation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Basic UVM concepts<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">4. Low-Power Concepts<\/span><\/h5><p><span style=\"font-weight: 400;\">Learn:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Dynamic power<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Leakage power<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock gating<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power gating<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multi-voltage design<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power domains<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">5. UPF<\/span><\/h5><p><span style=\"font-weight: 400;\">Then learn:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power domains<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Supply networks<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Isolation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Level shifting<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Retention<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power states<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power State Tables<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">UPF commands<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">6. Power-Aware Simulation<\/span><\/h5><p><span style=\"font-weight: 400;\">Finally, practice complete power-state transitions and debug failures.<\/span><\/p><p><span style=\"font-weight: 400;\">This progression is much easier than starting by memorizing UPF syntax.<\/span><\/p><p>\u00a0<\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">Low-power verification with UPF is about verifying that a design remains functionally correct while its power architecture changes.<\/span><\/p><p><span style=\"font-weight: 400;\">The most important concepts for a beginner are:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power domains<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power supplies<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Isolation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Level shifters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Retention<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power states<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power State Tables<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power-down and wake-up sequences<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power-aware simulation<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The key idea to remember is:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL tells you how the logic behaves. UPF tells you how the power architecture affects that logic.<\/span><\/p><p><span style=\"font-weight: 400;\">Once you understand that distinction, UPF becomes much easier to learn.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers moving toward SoC integration, RTL integration, or verification, learning UPF alongside functional verification provides a useful foundation for understanding modern multi-power-domain designs.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Modern SoCs rarely operate with a single power supply or a single operating mode. Different blocks may run at different voltages, some blocks may be switched off when they are not required, and important register states may need to be preserved during power-down. These techniques help reduce power consumption, but they also introduce new verification [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10170","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Low-Power Verification with UPF: Beginner&#039;s Guide<\/title>\n<meta name=\"description\" content=\"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Low-Power Verification with UPF: Beginner&#039;s Guide\" \/>\n<meta property=\"og:description\" content=\"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\" \/>\n<meta property=\"og:site_name\" content=\"Inskill VLSIGURU Elearning Platform\" \/>\n<meta property=\"article:published_time\" content=\"2026-09-14T11:01:00+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-09-15T11:09:40+00:00\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"9 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f\"},\"headline\":\"Low-Power Verification with UPF: A Beginner&#8217;s Introduction\",\"datePublished\":\"2026-09-14T11:01:00+00:00\",\"dateModified\":\"2026-09-15T11:09:40+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\"},\"wordCount\":1771,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\/\/inskill.in\/training\/#organization\"},\"articleSection\":[\"VLSI\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\",\"url\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\",\"name\":\"Low-Power Verification with UPF: Beginner's Guide\",\"isPartOf\":{\"@id\":\"https:\/\/inskill.in\/training\/#website\"},\"datePublished\":\"2026-09-14T11:01:00+00:00\",\"dateModified\":\"2026-09-15T11:09:40+00:00\",\"description\":\"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.\",\"breadcrumb\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/inskill.in\/training\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Low-Power Verification with UPF: A Beginner&#8217;s Introduction\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/inskill.in\/training\/#website\",\"url\":\"https:\/\/inskill.in\/training\/\",\"name\":\"Inskill VLSIGURU Elearning Platform\",\"description\":\"Best VLSI Training Institute\",\"publisher\":{\"@id\":\"https:\/\/inskill.in\/training\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/inskill.in\/training\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/inskill.in\/training\/#organization\",\"name\":\"Inskill VLSIGURU Elearning Platform\",\"url\":\"https:\/\/inskill.in\/training\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png\",\"contentUrl\":\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png\",\"width\":207,\"height\":89,\"caption\":\"Inskill VLSIGURU Elearning Platform\"},\"image\":{\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f\",\"name\":\"admin\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g\",\"caption\":\"admin\"},\"sameAs\":[\"https:\/\/inskill.in\/training\"],\"url\":\"https:\/\/inskill.in\/training\/author\/admin\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Low-Power Verification with UPF: Beginner's Guide","description":"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/","og_locale":"en_US","og_type":"article","og_title":"Low-Power Verification with UPF: Beginner's Guide","og_description":"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.","og_url":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/","og_site_name":"Inskill VLSIGURU Elearning Platform","article_published_time":"2026-09-14T11:01:00+00:00","article_modified_time":"2026-09-15T11:09:40+00:00","author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Est. reading time":"9 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#article","isPartOf":{"@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/"},"author":{"name":"admin","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f"},"headline":"Low-Power Verification with UPF: A Beginner&#8217;s Introduction","datePublished":"2026-09-14T11:01:00+00:00","dateModified":"2026-09-15T11:09:40+00:00","mainEntityOfPage":{"@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/"},"wordCount":1771,"commentCount":0,"publisher":{"@id":"https:\/\/inskill.in\/training\/#organization"},"articleSection":["VLSI"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/","url":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/","name":"Low-Power Verification with UPF: Beginner's Guide","isPartOf":{"@id":"https:\/\/inskill.in\/training\/#website"},"datePublished":"2026-09-14T11:01:00+00:00","dateModified":"2026-09-15T11:09:40+00:00","description":"Learn low-power verification with UPF, including power domains, isolation, retention, level shifters, power states and power-aware simulation.","breadcrumb":{"@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/inskill.in\/training\/"},{"@type":"ListItem","position":2,"name":"Low-Power Verification with UPF: A Beginner&#8217;s Introduction"}]},{"@type":"WebSite","@id":"https:\/\/inskill.in\/training\/#website","url":"https:\/\/inskill.in\/training\/","name":"Inskill VLSIGURU Elearning Platform","description":"Best VLSI Training Institute","publisher":{"@id":"https:\/\/inskill.in\/training\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/inskill.in\/training\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/inskill.in\/training\/#organization","name":"Inskill VLSIGURU Elearning Platform","url":"https:\/\/inskill.in\/training\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/","url":"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png","contentUrl":"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png","width":207,"height":89,"caption":"Inskill VLSIGURU Elearning Platform"},"image":{"@id":"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f","name":"admin","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g","caption":"admin"},"sameAs":["https:\/\/inskill.in\/training"],"url":"https:\/\/inskill.in\/training\/author\/admin\/"}]}},"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10170","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/comments?post=10170"}],"version-history":[{"count":4,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10170\/revisions"}],"predecessor-version":[{"id":10176,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10170\/revisions\/10176"}],"wp:attachment":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/media?parent=10170"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/categories?post=10170"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/tags?post=10170"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}