{"id":10188,"date":"2026-09-18T10:16:14","date_gmt":"2026-09-18T10:16:14","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10188"},"modified":"2026-09-17T10:18:40","modified_gmt":"2026-09-17T10:18:40","slug":"vlsi-engineers-should-know-about-pcie-before-working-on-socs","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/vlsi-engineers-should-know-about-pcie-before-working-on-socs\/","title":{"rendered":"What VLSI Engineers Should Know About PCIe Before Working on SoCs"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10188\" class=\"elementor elementor-10188\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-012627f elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"012627f\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-b8f517e\" data-id=\"b8f517e\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-1a5654a elementor-widget elementor-widget-text-editor\" data-id=\"1a5654a\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">PCI Express, commonly called <\/span><b>PCIe<\/b><span style=\"font-weight: 400;\">, is one of the most important high-speed interconnect technologies used in modern computing systems. It connects processors with devices such as GPUs, storage controllers, network adapters, accelerators and other high-performance peripherals.<\/span><\/p><p><span style=\"font-weight: 400;\">For a VLSI engineer working on a modern SoC, simply knowing that PCIe is a \u201chigh-speed serial protocol\u201d is not enough.<\/span><\/p><p><span style=\"font-weight: 400;\">Engineers working on PCIe IP, SoC integration, RTL design, functional verification, validation or system-level debugging need to understand how the protocol is organized, how packets move through its layers, how links are initialized, how devices are discovered and configured, and how errors and power states are handled.<\/span><\/p><p><span style=\"font-weight: 400;\">The PCI-SIG PCI Express Base specification defines the architecture, interconnect attributes, fabric management and programming interfaces required for compliant PCIe systems and peripherals. The current approved base specification is Revision 7.0.<\/span><\/p><p><span style=\"font-weight: 400;\">This guide explains the PCIe concepts VLSI engineers should understand before working on SoCs, without requiring them to memorize the entire specification.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why Should VLSI Engineers Learn PCIe?<\/span><\/h3><p><span style=\"font-weight: 400;\">Modern SoCs contain multiple high-speed interfaces and increasingly complex subsystems.<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe is commonly encountered in systems involving:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">CPUs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">GPUs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AI accelerators<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">NVMe storage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Ethernet controllers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Network accelerators<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FPGA accelerators<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DMA engines<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe switches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">High-performance computing systems<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">PCI-SIG identifies data centers, AI\/ML, HPC, networking, storage, automotive and other data-intensive applications among the areas using PCIe technology.<\/span><\/p><p><span style=\"font-weight: 400;\">For a VLSI engineer, PCIe knowledge becomes particularly useful when working on:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe controller RTL<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol verification<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SoC integration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe PHY interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">UVM verification environments<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DMA<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory-mapped I\/O<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interrupt mechanisms<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link training<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power management<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error handling<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Silicon validation<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Inskill&#8217;s PCIe training material similarly covers the Transaction, Data Link and Physical layers along with packet formats, flow control, error handling, link management, timing and waveform debugging.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Is More Than a Physical Interface<\/span><\/h3><p><span style=\"font-weight: 400;\">A common beginner mistake is to think of PCIe as simply a group of high-speed differential signals.<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe is a complete communication architecture.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified view is:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PCIe Device<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0| Transaction Layer|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0| \u00a0 Data Link\u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0|\u00a0 \u00a0 \u00a0 Layer \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0| Physical Layer \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PCIe Link<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Each layer performs a different function.<\/span><\/p><p><span style=\"font-weight: 400;\">Understanding these layers is one of the first things an engineer should learn.<\/span><\/p><h3><span style=\"font-weight: 400;\">1. PCIe Transaction Layer<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><b>Transaction Layer<\/b><span style=\"font-weight: 400;\"> deals with the actual requests and completions exchanged between PCIe components.<\/span><\/p><p><span style=\"font-weight: 400;\">This is where concepts such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory Read<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory Write<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration Read<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration Write<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Completion<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Message transactions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">become important.<\/span><\/p><p><span style=\"font-weight: 400;\">Transactions are represented using <\/span><b>Transaction Layer Packets (TLPs)<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Requester<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0| Memory Read TLP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Completer<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0| Completion TLP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Requester<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">For a VLSI engineer, it is important to understand that a PCIe transaction is not simply \u201cdata going from A to B.\u201d<\/span><\/p><p><span style=\"font-weight: 400;\">The transaction has attributes, addressing information, request\/completion behavior and protocol rules that determine how it should be handled.<\/span><\/p><h5><span style=\"font-weight: 400;\">Why TLP knowledge matters<\/span><\/h5><p><span style=\"font-weight: 400;\">If you work in PCIe verification, you may need to:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Generate TLPs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Decode TLPs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Check TLP fields<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Track requests and completions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Verify ordering<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Check packet attributes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Debug packet-level failures<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">If you work in RTL design, you may encounter logic that generates, processes, buffers or routes these transactions.<\/span><\/p><h3><span style=\"font-weight: 400;\">2. PCIe Data Link Layer<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><b>Data Link Layer<\/b><span style=\"font-weight: 400;\"> provides reliable delivery across a PCIe link.<\/span><\/p><p><span style=\"font-weight: 400;\">It is concerned with mechanisms such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Packet integrity<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Sequence tracking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error detection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Acknowledgment<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Retry\/replay<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flow-control information<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A simplified view is:<\/span><\/p><p><span style=\"font-weight: 400;\">Transaction Layer<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0TLP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Data Link Layer<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0Reliability<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Physical Layer<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The Data Link Layer is particularly important when debugging situations where packets are generated correctly at the transaction level but something goes wrong while transferring them across the link.<\/span><\/p><p><span style=\"font-weight: 400;\">A VLSI verification engineer should understand the relationship between TLPs and Data Link Layer mechanisms rather than treating them as independent protocols.<\/span><\/p><h3><span style=\"font-weight: 400;\">3. PCIe Physical Layer<\/span><\/h3><p><span style=\"font-weight: 400;\">The Physical Layer is responsible for transmitting and receiving information over the actual PCIe link.<\/span><\/p><p><span style=\"font-weight: 400;\">At a high level, it deals with:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lanes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Electrical signaling<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Encoding\/modulation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link initialization<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Training<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane management<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Equalization<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Receiver detection<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The Physical Layer becomes increasingly complex as PCIe generations increase their data rates.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, PCIe 6.0 introduced <\/span><b>64.0 GT\/s<\/b><span style=\"font-weight: 400;\">, PAM4 signaling, FEC and fixed-size 256-byte Flits.<\/span><\/p><p><span style=\"font-weight: 400;\">The key lesson for a VLSI engineer is that PCIe generations are not simply \u201cthe same protocol but faster.\u201d Higher generations introduce additional electrical and encoding requirements that affect the implementation and verification environment.<\/span><\/p><h3><span style=\"font-weight: 400;\">Understanding PCIe Lanes<\/span><\/h3><p><span style=\"font-weight: 400;\">A PCIe link consists of one or more lanes.<\/span><\/p><p><span style=\"font-weight: 400;\">Common configurations include:<\/span><\/p><p><span style=\"font-weight: 400;\">x1<\/span><\/p><p><span style=\"font-weight: 400;\">x2<\/span><\/p><p><span style=\"font-weight: 400;\">x4<\/span><\/p><p><span style=\"font-weight: 400;\">x8<\/span><\/p><p><span style=\"font-weight: 400;\">x16<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A lane contains differential transmit and receive paths.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">Device A\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Device B<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0TX\u00a0 &#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-&gt; RX<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0RX\u00a0 &lt;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-\u00a0 TX<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">With multiple lanes:<\/span><\/p><p><span style=\"font-weight: 400;\">Lane 0<\/span><\/p><p><span style=\"font-weight: 400;\">Lane 1<\/span><\/p><p><span style=\"font-weight: 400;\">Lane 2<\/span><\/p><p><span style=\"font-weight: 400;\">Lane 3<\/span><\/p><p><span style=\"font-weight: 400;\">&#8230;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The number of lanes affects aggregate link bandwidth.<\/span><\/p><p><span style=\"font-weight: 400;\">An engineer working on PCIe should understand the distinction between:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">x1\/x4\/x8\/x16 configuration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane numbering<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane polarity<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane reversal<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">These concepts become particularly important when working closer to the Physical Layer.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a PCIe Root Complex?<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><b>Root Complex (RC)<\/b><span style=\"font-weight: 400;\"> provides the connection between the processor\/system memory side and the PCIe hierarchy.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified system may look like:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0CPU<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Root Complex<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;-+&#8212;&#8212;-+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Endpoint \u00a0 \u00a0 \u00a0 \u00a0 Switch<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;-+&#8212;-+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Endpoint \u00a0 Endpoint<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The Root Complex is an important concept for SoC engineers because it is typically where PCIe connects into the host system architecture.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a PCIe Endpoint?<\/span><\/h3><p><span style=\"font-weight: 400;\">A PCIe <\/span><b>Endpoint<\/b><span style=\"font-weight: 400;\"> is a device that participates in the PCIe hierarchy as an endpoint rather than as the root.<\/span><\/p><p><span style=\"font-weight: 400;\">Examples can include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SSD controllers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Network adapters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Accelerators<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FPGA cards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe peripherals<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">From a verification perspective, the role of the device matters because the expected transactions and configuration behavior depend on whether the component is functioning as a Root Complex, Endpoint, Switch or another PCIe component.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a PCIe Switch?<\/span><\/h3><p><span style=\"font-weight: 400;\">A PCIe switch allows PCIe traffic to be connected across multiple downstream ports.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Root Complex<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Switch<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\u00a0 \u00a0 |\u00a0 \u00a0 \\<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/ \u00a0 \u00a0 | \u00a0 \u00a0 \\<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0EP1 \u00a0 \u00a0 EP2 \u00a0 \u00a0 EP3<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Understanding the topology is important for SoC and system-level engineers because packet routing and hierarchy become more complex when multiple devices are involved.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is LTSSM?<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the most important concepts for a PCIe engineer is the Link Training and Status State Machine, commonly called LTSSM.<\/span><\/p><p><span style=\"font-weight: 400;\">The LTSSM controls and monitors the process through which a PCIe link moves from an inactive state toward normal operation and through various recovery or low-power conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified conceptual flow is:<\/span><\/p><p><span style=\"font-weight: 400;\">Detect<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Polling<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Configuration<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">L0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There are additional states and transitions involved in actual PCIe operation.<\/span><\/p><p><span style=\"font-weight: 400;\">The important idea is that the link does not simply become active as soon as power is applied.<\/span><\/p><p><span style=\"font-weight: 400;\">The two ends must detect each other, exchange training information, establish the required configuration and reach an operational state.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why LTSSM matters in VLSI work<\/span><\/h3><p><span style=\"font-weight: 400;\">LTSSM is important for:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe RTL design<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Verification<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol debugging<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link bring-up<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Silicon validation<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example, if a PCIe link refuses to reach <\/span><span style=\"font-weight: 400;\">L0<\/span><span style=\"font-weight: 400;\">, an engineer needs to determine where the state-machine progression stopped.<\/span><\/p><p><span style=\"font-weight: 400;\">That makes LTSSM knowledge extremely valuable during waveform debugging.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is PCIe Link Training?<\/span><\/h3><p><span style=\"font-weight: 400;\">Before normal data traffic can occur, the link needs to establish communication between its two ends.<\/span><\/p><p><span style=\"font-weight: 400;\">Training involves mechanisms that allow the link partners to determine and establish appropriate operating conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">Depending on the PCIe generation and implementation, engineers may encounter concepts such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Receiver detection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Training sequences<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane configuration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Speed negotiation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link-width negotiation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Equalization<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Recovery<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For a VLSI engineer, link training should be understood as a <\/span><b>sequence of protocol and physical-layer events<\/b><span style=\"font-weight: 400;\">, not just as a single initialization signal.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe TLPs: What Engineers Should Know<\/span><\/h3><p><span style=\"font-weight: 400;\">TLPs are fundamental to understanding PCIe transactions.<\/span><\/p><p><span style=\"font-weight: 400;\">At a conceptual level, a TLP can contain:<\/span><\/p><p><span style=\"font-weight: 400;\">+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-+<\/span><\/p><p><span style=\"font-weight: 400;\">| Header\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-+<\/span><\/p><p><span style=\"font-weight: 400;\">| Optional Data \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">+&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-+<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The header describes the transaction.<\/span><\/p><p><span style=\"font-weight: 400;\">Depending on the transaction type, the TLP may carry information such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Request type<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Length<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Requester information<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Attributes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Completion information<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A verification engineer does not necessarily need to memorize every field initially.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead, learn to answer:<\/span><\/p><p><b>What transaction is this? Who generated it? Who should respond? What does the receiver do with it?<\/b><\/p><p><span style=\"font-weight: 400;\">That way of thinking becomes much more useful when debugging waveforms.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Are DLLPs?<\/span><\/h3><p><b>Data Link Layer Packets (DLLPs)<\/b><span style=\"font-weight: 400;\"> are associated with Data Link Layer functions.<\/span><\/p><p><span style=\"font-weight: 400;\">They support link-level mechanisms such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flow control<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Acknowledgment<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Negative acknowledgment\/retry-related behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power management functions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The distinction is important:<\/span><\/p><p><span style=\"font-weight: 400;\">TLP\u00a0 \u2192 Transaction Layer<\/span><\/p><p><span style=\"font-weight: 400;\">DLLP \u2192 Data Link Layer<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">In PCIe 6.0 Flit Mode, TLPs and DLLPs are carried within fixed-size Flits rather than using the older packet framing arrangement. PCI-SIG specifies a 256-byte Flit structure for PCIe 6.0 Flit Mode.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Configuration Space and Enumeration<\/span><\/h3><p><span style=\"font-weight: 400;\">A PCIe device needs to be discovered and configured before normal system operation.<\/span><\/p><p><span style=\"font-weight: 400;\">This is where concepts such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration space<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Vendor ID<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Device ID<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">BARs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Capabilities<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Bus\/device\/function addressing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Enumeration<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">become important.<\/span><\/p><h5><span style=\"font-weight: 400;\">What is enumeration?<\/span><\/h5><p><span style=\"font-weight: 400;\">At a high level, the host discovers the PCIe hierarchy and determines what devices are present and what resources they require.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified flow is:<\/span><\/p><p><span style=\"font-weight: 400;\">System starts<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Discover PCIe hierarchy<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Identify devices<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Read configuration information<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Assign resources<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Enable devices<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Normal operation<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A VLSI engineer working on a PCIe Endpoint should understand what configuration information the device exposes and how the host interacts with it.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Are BARs?<\/span><\/h3><p><b>Base Address Registers (BARs)<\/b><span style=\"font-weight: 400;\"> are used to describe addressable regions associated with a PCIe function.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a device might expose registers that the host accesses through a memory-mapped address region.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">CPU<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0| Memory-mapped access<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe Root Complex<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe Endpoint<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Device Registers<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Understanding BARs helps engineers connect the PCIe protocol with the broader SoC memory-mapped architecture.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Flow Control<\/span><\/h3><p><span style=\"font-weight: 400;\">PCIe needs mechanisms to prevent receivers from being overwhelmed by traffic.<\/span><\/p><p><span style=\"font-weight: 400;\">Flow control is therefore an important topic for both design and verification engineers.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified concept is:<\/span><\/p><p><span style=\"font-weight: 400;\">Sender<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0| Data<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Receiver Buffer<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0| Available space?<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Flow Control<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Engineers should understand the relationship between:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Credits<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Buffers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">TLP transmission<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Receiver availability<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The exact implementation details depend on the PCIe generation and protocol mode.<\/span><\/p><p><span style=\"font-weight: 400;\">For interviews and initial project work, understanding why flow control exists and how it prevents buffer overflow is more important than memorizing every credit field.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Error Handling<\/span><\/h3><p><span style=\"font-weight: 400;\">High-speed interfaces need mechanisms to detect and respond to errors.<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe includes multiple error-handling mechanisms across its layers.<\/span><\/p><p><span style=\"font-weight: 400;\">At a high level, engineers should understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error detection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">CRC<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Retry\/replay<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Correctable errors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Uncorrectable errors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error reporting<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Recovery<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">PCIe 6.0 introduced FEC alongside CRC to address the higher error characteristics associated with PAM4 signaling.<\/span><\/p><p><span style=\"font-weight: 400;\">For a verification engineer, error injection is particularly useful.<\/span><\/p><p><span style=\"font-weight: 400;\">A good PCIe verification environment should not test only successful transactions. It should also exercise error scenarios and verify that the design responds according to the intended protocol behavior.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Power Management<\/span><\/h3><p><span style=\"font-weight: 400;\">SoC engineers should also understand PCIe power states.<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe systems can enter lower-power conditions when full link activity is unnecessary.<\/span><\/p><p><span style=\"font-weight: 400;\">This introduces another verification dimension:<\/span><\/p><p><span style=\"font-weight: 400;\">Active<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Low Power<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Wake-up<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Active<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The engineer needs to consider:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link state transitions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power-management requests<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Wake-up behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data preservation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Recovery<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This becomes particularly important in mobile, embedded and power-sensitive SoCs.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe and DMA<\/span><\/h3><p><span style=\"font-weight: 400;\">PCIe is frequently associated with high-throughput data movement, so DMA (Direct Memory Access) is an important adjacent concept.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified data path might look like:<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe Device<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe Controller<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">DMA Engine<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">System Memory<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Instead of requiring the CPU to move every data word, a DMA engine can coordinate transfers between device and memory.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, understanding the interaction between PCIe, DMA, memory addressing and interrupts helps connect protocol-level knowledge to actual SoC architecture.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Should a PCIe RTL Engineer Know?<\/span><\/h3><p><span style=\"font-weight: 400;\">An RTL engineer working on PCIe should build knowledge in several layers.<\/span><\/p><h5><span style=\"font-weight: 400;\">Digital design<\/span><\/h5><p><span style=\"font-weight: 400;\">You should be comfortable with:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM design<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFOs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Handshaking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Arbitration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Counters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Buffers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock-domain crossing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset design<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Protocol concepts<\/span><\/h5><p><span style=\"font-weight: 400;\">You should understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">TLPs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DLLPs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flow control<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">LTSSM<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error handling<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power states<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">PCIe architecture<\/span><\/h5><p><span style=\"font-weight: 400;\">You should know:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Root Complex<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Endpoint<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Switch<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe hierarchy<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Debugging<\/span><\/h5><p><span style=\"font-weight: 400;\">You should be able to inspect a waveform and reason about:<\/span><\/p><p><span style=\"font-weight: 400;\">Transaction<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Packet<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Protocol state<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Link state<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Expected response<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">What Should a PCIe Verification Engineer Know?<\/span><\/h3><p><span style=\"font-weight: 400;\">A verification engineer needs an additional layer of knowledge.<\/span><\/p><p><span style=\"font-weight: 400;\">You should understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SystemVerilog<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">UVM<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Sequence generation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">TLP generation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Monitors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Functional coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error injection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol checking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Waveform analysis<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A typical PCIe verification environment may conceptually look like:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Test<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Sequence<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Driver<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PCIe DUT<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;+&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Monitor\u00a0 \u00a0 \u00a0 Monitor<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;+&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Scoreboard<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Coverage<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Inskill&#8217;s PCIe Transaction Layer training specifically includes UVC\/testbench development, while its Data Link Layer training focuses on DLL verification and testbench development.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Should an SoC Integration Engineer Know?<\/span><\/h3><p><span style=\"font-weight: 400;\">An SoC integration engineer does not necessarily need to implement every PCIe protocol block from scratch.<\/span><\/p><p><span style=\"font-weight: 400;\">However, they should understand how PCIe connects with the rest of the chip.<\/span><\/p><p><span style=\"font-weight: 400;\">Important areas include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AXI or internal SoC interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock and reset domains<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DMA<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interrupts<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory map<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address translation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power management<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">PCIe PHY interface<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration registers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error reporting<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A simplified SoC integration view is:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0CPU<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0AXI \/ NoC<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;+&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0Memory\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 PCIe<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0Controller\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Controller<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PHY<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PCIe Link<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact architecture varies by SoC, but the integration principle remains similar: PCIe is one subsystem within a larger hardware and software architecture.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe Generations: What Should Engineers Know?<\/span><\/h3><p><span style=\"font-weight: 400;\">Engineers frequently encounter PCIe Gen3, Gen4, Gen5 and Gen6 in real projects.<\/span><\/p><p><span style=\"font-weight: 400;\">The important thing is to understand the progression rather than memorizing numbers without context.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><table><tbody><tr><td><p><b>Generation<\/b><\/p><\/td><td><p><b>Key point<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen1<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">2.5 GT\/s<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen2<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">5.0 GT\/s<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen3<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">8.0 GT\/s<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen4<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">16.0 GT\/s<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen5<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">32.0 GT\/s<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Gen6<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">64.0 GT\/s, PAM4 and Flit Mode<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">PCI-SIG confirms that PCIe 6.0 doubles the 32 GT\/s rate of PCIe 5.0 to 64 GT\/s and introduces PAM4, FEC and Flit Mode.<\/span><\/p><p><span style=\"font-weight: 400;\">However, GT\/s is not the same thing as application-level GB\/s. Encoding, protocol overhead, lane count and implementation details affect usable bandwidth.<\/span><\/p><p><span style=\"font-weight: 400;\">This distinction is important in technical interviews.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe 5.0 vs PCIe 6.0: Why the Difference Matters<\/span><\/h3><p><span style=\"font-weight: 400;\">A beginner might assume:<\/span><\/p><p><span style=\"font-weight: 400;\">\u201cPCIe 6.0 is just PCIe 5.0 running twice as fast.\u201d<\/span><\/p><p><span style=\"font-weight: 400;\">That is an incomplete understanding.<\/span><\/p><p><span style=\"font-weight: 400;\">PCIe 6.0 introduced a major change in signaling with <\/span><b>PAM4<\/b><span style=\"font-weight: 400;\">, along with FEC and CRC mechanisms and Flit-based operation.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore, engineers working on newer PCIe designs need to understand how changes at the Physical Layer influence the rest of the implementation and verification flow.<\/span><\/p><h3><span style=\"font-weight: 400;\">PCIe and CXL<\/span><\/h3><p><span style=\"font-weight: 400;\">Engineers entering modern SoC and data-center designs may also encounter <\/span><b>CXL (Compute Express Link)<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">PCI-SIG notes that protocols such as CXL and NVMe leverage PCIe infrastructure and PHY technology.<\/span><\/p><p><span style=\"font-weight: 400;\">This does not mean PCIe and CXL are the same protocol.<\/span><\/p><p><span style=\"font-weight: 400;\">Rather, knowledge of PCIe provides useful background for understanding other high-speed interconnect technologies.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Should You Learn First?<\/span><\/h3><p><span style=\"font-weight: 400;\">If you are new to PCIe, avoid trying to read the complete specification from the first page.<\/span><\/p><p><span style=\"font-weight: 400;\">A practical learning order is:<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Understand the architecture<\/span><\/h5><p><span style=\"font-weight: 400;\">Learn:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Root Complex<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Endpoint<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Switch<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Lane<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 2: Learn the three major layers<\/span><\/h5><p><span style=\"font-weight: 400;\">Understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Transaction Layer<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data Link Layer<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Physical Layer<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 3: Learn TLPs<\/span><\/h5><p><span style=\"font-weight: 400;\">Start with:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory Read<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory Write<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Completion<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration transactions<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 4: Learn link operation<\/span><\/h5><p><span style=\"font-weight: 400;\">Study:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">LTSSM<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link training<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Link states<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Recovery<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Equalization<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 5: Learn configuration<\/span><\/h5><p><span style=\"font-weight: 400;\">Study:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Configuration space<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Enumeration<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">BARs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Capabilities<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 6: Learn reliability<\/span><\/h5><p><span style=\"font-weight: 400;\">Understand:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flow control<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">CRC<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Replay<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error handling<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 7: Learn verification<\/span><\/h5><p><span style=\"font-weight: 400;\">Practice:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">TLP generation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error injection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Waveform debugging<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 8: Connect PCIe to SoC architecture<\/span><\/h5><p><span style=\"font-weight: 400;\">Finally, learn how PCIe interacts with:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">CPU<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">DMA<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AXI\/NoC<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interrupts<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock\/reset<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power management<\/span><\/li><\/ul><p>\u00a0<\/p><h2><b>Final Takeaway<\/b><\/h2><p><span style=\"font-weight: 400;\">A VLSI engineer does not need to memorize the entire PCIe specification before working on a PCIe-based SoC.<\/span><\/p><p><span style=\"font-weight: 400;\">What matters first is understanding <\/span><b>how the pieces fit together<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Start with the architecture.<\/span> <span style=\"font-weight: 400;\">Then understand the protocol and then move into the mechanisms. Finally, connect PCIe to the SoC. That foundation gives RTL designers, verification engineers and SoC integration engineers the context they need to understand PCIe-based projects and debug problems more effectively.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>PCI Express, commonly called PCIe, is one of the most important high-speed interconnect technologies used in modern computing systems. It connects processors with devices such as GPUs, storage controllers, network adapters, accelerators and other high-performance peripherals. For a VLSI engineer working on a modern SoC, simply knowing that PCIe is a \u201chigh-speed serial protocol\u201d is [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10188","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>PCIe for VLSI Engineers: What SoC Designers Should Know<\/title>\n<meta name=\"description\" content=\"Learn the PCIe concepts VLSI and SoC engineers need, including layers, TLPs, LTSSM, link training, configuration, flow control, errors and verification.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" 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