{"id":10195,"date":"2026-09-21T13:23:06","date_gmt":"2026-09-21T13:23:06","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10195"},"modified":"2026-09-21T13:23:49","modified_gmt":"2026-09-21T13:23:49","slug":"synthesis-friendly-technology-agnostic-rtl","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/synthesis-friendly-technology-agnostic-rtl\/","title":{"rendered":"How to Make RTL Code Synthesis-Friendly and Technology-Agnostic"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10195\" class=\"elementor elementor-10195\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-c2df672 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"c2df672\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-8cd9e4e\" data-id=\"8cd9e4e\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-bca47d8 elementor-widget elementor-widget-text-editor\" data-id=\"bca47d8\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">Writing RTL that produces the expected simulation result is only one part of digital design.<\/span><\/p><p><span style=\"font-weight: 400;\">For an RTL design to be useful in an ASIC or SoC development flow, it must also describe hardware clearly enough for synthesis tools to convert it into the intended gate-level implementation. At the same time, reusable RTL should avoid unnecessary dependence on a particular standard-cell library, technology node, or implementation tool.<\/span><\/p><p><span style=\"font-weight: 400;\">This is where <\/span><b>synthesis-friendly and technology-agnostic RTL<\/b><span style=\"font-weight: 400;\"> becomes important.<\/span><\/p><p><span style=\"font-weight: 400;\">A synthesis-friendly design uses coding constructs and structures that map predictably to hardware. A technology-agnostic design keeps the functional RTL independent of implementation-specific cells and libraries wherever possible.<\/span><\/p><p><span style=\"font-weight: 400;\">These principles are closely related, but they are not exactly the same.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, code can be synthesizable but still contain technology-specific primitives. Conversely, code can look portable but accidentally infer a latch or create an unintended combinational path.<\/span><\/p><p><span style=\"font-weight: 400;\">This guide explains how to write RTL that is <\/span><b>synthesizable, portable, readable, reusable, and easier to verify<\/b><span style=\"font-weight: 400;\">, with practical Verilog and SystemVerilog examples.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Does Synthesis-Friendly RTL Mean?<\/span><\/h3><p><b>Synthesis-friendly RTL<\/b><span style=\"font-weight: 400;\"> is RTL written so that synthesis tools can reliably infer the intended hardware structure.<\/span><\/p><p><span style=\"font-weight: 400;\">The RTL should make it reasonably clear whether the designer intends to create:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Combinational logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flip-flops<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Registers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiplexers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Counters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memories<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSMs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Arithmetic logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock enables<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Other supported hardware structures<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example, this sequential block clearly describes register behavior:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (en)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0data_q &lt;= data_d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The intended hardware is straightforward:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;+<\/span><\/p><p><span style=\"font-weight: 400;\">data_d &#8212;&#8211;&gt;| \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 FF\u00a0 \u00a0 |&#8212;-&gt; data_q<\/span><\/p><p><span style=\"font-weight: 400;\">clk &#8212;&#8212;&#8211;&gt;| \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">en &#8212;&#8212;&#8212;&gt;| \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0+&#8212;&#8212;&#8212;+<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The goal is not to write RTL that forces a particular gate implementation. The goal is to describe the required hardware behavior clearly and let synthesis perform the technology-specific optimization.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Does Technology-Agnostic RTL Mean?<\/span><\/h3><p><b>Technology-agnostic RTL<\/b><span style=\"font-weight: 400;\"> is functional RTL that does not unnecessarily depend on a specific semiconductor technology or standard-cell library.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, generic RTL should normally describe:<\/span><\/p><p><span style=\"font-weight: 400;\">AND behavior<\/span><\/p><p><span style=\"font-weight: 400;\">OR behavior<\/span><\/p><p><span style=\"font-weight: 400;\">multiplexing<\/span><\/p><p><span style=\"font-weight: 400;\">registers<\/span><\/p><p><span style=\"font-weight: 400;\">arithmetic<\/span><\/p><p><span style=\"font-weight: 400;\">state machines<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">rather than directly instantiating a library-specific cell everywhere.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of writing technology-dependent logic such as:<\/span><\/p><p><span style=\"font-weight: 400;\">MY_7NM_SPECIAL_MUX u_mux (&#8230;);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">a reusable RTL block can describe the intended behavior:<\/span><\/p><p><span style=\"font-weight: 400;\">assign y = sel ? b : a;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The synthesis flow can then map that behavior to cells available in the target technology.<\/span><\/p><p><span style=\"font-weight: 400;\">Technology-independent RTL is particularly useful when the same functional IP may be synthesized for different technologies, libraries or implementation targets. Industry RTL guidance also recommends separating technology-dependent elements from reusable core logic.<\/span><\/p><h3><span style=\"font-weight: 400;\">Synthesis-Friendly vs Technology-Agnostic RTL<\/span><\/h3><p><span style=\"font-weight: 400;\">These terms are related but should not be treated as synonyms.<\/span><\/p><table><tbody><tr><td><p><b>Synthesis-Friendly RTL<\/b><\/p><\/td><td><p><b>Technology-Agnostic RTL<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Focuses on predictable synthesis<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Focuses on portability<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Avoids unintended hardware<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Avoids unnecessary technology-specific implementation<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Prevents latch and inference problems<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Allows reuse across technologies<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Uses synthesis-supported constructs<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Avoids unnecessary library dependencies<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Considers timing, area and power implications<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Separates functional RTL from implementation-specific cells<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">Good RTL should ideally satisfy both goals.<\/span><\/p><h3><span style=\"font-weight: 400;\">1. Clearly Separate Combinational and Sequential Logic<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the simplest ways to make RTL easier to understand and synthesize is to clearly distinguish combinational logic from sequential logic.<\/span><\/p><p><span style=\"font-weight: 400;\">For sequential logic:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">For combinational logic:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = a &amp; b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">SystemVerilog&#8217;s <\/span><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> also provide stronger intent checking in supporting tools. For example, established RTL style guides recommend <\/span><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\"> for sequential logic and <\/span><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> for combinational logic.<\/span><\/p><p><span style=\"font-weight: 400;\">If a project uses Verilog rather than SystemVerilog, the equivalent conventional forms are:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(posedge clk)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><span style=\"font-weight: 400;\">always @(*)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The important principle is not the keyword itself.<\/span><\/p><p><span style=\"font-weight: 400;\">It is making the hardware intent unambiguous.<\/span><\/p><h3><span style=\"font-weight: 400;\">2. Avoid Unintended Latch Inference<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the most common RTL mistakes is accidentally describing a latch.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">What happens when <\/span><span style=\"font-weight: 400;\">enable<\/span><span style=\"font-weight: 400;\"> is <\/span><span style=\"font-weight: 400;\">0<\/span><span style=\"font-weight: 400;\">?<\/span><\/p><p><span style=\"font-weight: 400;\">There is no assignment to <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">The synthesis tool therefore needs some storage behavior to preserve the previous value, potentially resulting in latch inference.<\/span><\/p><p><span style=\"font-weight: 400;\">A safer combinational structure is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = &#8216;0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Or:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The general rule is:<\/span><\/p><p><span style=\"font-weight: 400;\">Every combinational output should receive a defined value for every possible execution path.<\/span><\/p><p><span style=\"font-weight: 400;\">Unintended latches can create timing and verification complications, which is why avoiding incomplete combinational assignments is a common synthesis guideline.<\/span><\/p><h3><span style=\"font-weight: 400;\">3. Use Non-Blocking Assignments for Clocked Logic<\/span><\/h3><p><span style=\"font-weight: 400;\">For clocked sequential logic, use non-blocking assignments:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q1 &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q2 &lt;= q1;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This represents two separate registers.<\/span><\/p><p><span style=\"font-weight: 400;\">Using blocking assignments in sequential logic can produce simulation behavior that does not reflect the intended register-to-register relationship.<\/span><\/p><p><span style=\"font-weight: 400;\">A simple rule for RTL coding is:<\/span><\/p><p><span style=\"font-weight: 400;\">Sequential logic \u00a0 \u00a0 \u2192 &lt;=<\/span><\/p><p><span style=\"font-weight: 400;\">Combinational logic\u00a0 \u2192 =<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact coding standard may vary between organizations, but consistency is essential.<\/span><\/p><h3><span style=\"font-weight: 400;\">4. Do Not Mix Combinational and Sequential Intent Carelessly<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = q &amp; mask;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The structure is easy to understand:<\/span><\/p><p><span style=\"font-weight: 400;\">d<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">[Register]<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0q<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Combinational Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0y<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Compare this with a large procedural block containing registers, combinational calculations, temporary variables and multiple control conditions.<\/span><\/p><p><span style=\"font-weight: 400;\">Large mixed blocks can become harder to review and debug.<\/span><\/p><p><span style=\"font-weight: 400;\">Good RTL organization should make the hardware structure visible from the code.<\/span><\/p><h3><span style=\"font-weight: 400;\">5. Avoid Simulation-Only Constructs in Synthesizable RTL<\/span><\/h3><p><span style=\"font-weight: 400;\">Not everything that can execute in a Verilog\/SystemVerilog simulator represents hardware.<\/span><\/p><p><span style=\"font-weight: 400;\">Common examples that generally belong in testbench or verification code rather than generic synthesizable RTL include:<\/span><\/p><p><span style=\"font-weight: 400;\">#10<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">simulation delays,<\/span><\/p><p><span style=\"font-weight: 400;\">$display(&#8230;)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><span style=\"font-weight: 400;\">initial begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0&#8230;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">depending on the target technology and synthesis flow.<\/span><\/p><p><span style=\"font-weight: 400;\">File I\/O, simulation control and timing delays are typically verification constructs rather than portable RTL.<\/span><\/p><p><span style=\"font-weight: 400;\">The distinction is important:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Hardware description<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Synthesis<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Gate-level implementation<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">versus:<\/span><\/p><p><span style=\"font-weight: 400;\">Testbench<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Simulation control<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Stimulus \/ checking<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Do not confuse what a simulator can execute with what a synthesis flow can implement as hardware. Current synthesis guidance continues to distinguish synthesis-supported constructs from simulation-only constructs such as delays and system tasks.<\/span><\/p><h3><span style=\"font-weight: 400;\">6. Make Widths Explicit<\/span><\/h3><p><span style=\"font-weight: 400;\">Width mismatches can produce subtle RTL bugs.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] a;<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] b;<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] result;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assign result = a + b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Now consider an expression involving different widths:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0]\u00a0 a;<\/span><\/p><p><span style=\"font-weight: 400;\">logic [15:0] b;<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0]\u00a0 result;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The result may be truncated depending on the expression and assignment context.<\/span><\/p><p><span style=\"font-weight: 400;\">A synthesis-friendly coding style should make widths intentional.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [15:0] sum;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assign sum = {8&#8217;b0, a} + b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Explicit widths make the designer&#8217;s intention easier to review and reduce surprises from implicit sizing and signedness rules.<\/span><\/p><h3><span style=\"font-weight: 400;\">7. Be Careful With Signed and Unsigned Arithmetic<\/span><\/h3><p><span style=\"font-weight: 400;\">Signedness can change arithmetic and comparison behavior.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] a;<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assign greater = (a &gt; b);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Both signals are unsigned unless declared otherwise.<\/span><\/p><p><span style=\"font-weight: 400;\">If signed arithmetic is required, state that intention explicitly:<\/span><\/p><p><span style=\"font-weight: 400;\">logic signed [7:0] a;<\/span><\/p><p><span style=\"font-weight: 400;\">logic signed [7:0] b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Do not assume that the synthesis tool will interpret arithmetic based on what the designer intended.<\/span><\/p><p><span style=\"font-weight: 400;\">The RTL should express the intended data type clearly.<\/span><\/p><h3><span style=\"font-weight: 400;\">8. Use Parameters Instead of Hardcoding Repeated Design Values<\/span><\/h3><p><span style=\"font-weight: 400;\">Technology-agnostic RTL should also be reusable.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider a fixed-width counter:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] count;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If the design later needs a 16-bit counter, the module may need to be modified.<\/span><\/p><p><span style=\"font-weight: 400;\">A parameterized implementation is more reusable:<\/span><\/p><p><span style=\"font-weight: 400;\">module counter #(<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0parameter int WIDTH = 8<\/span><\/p><p><span style=\"font-weight: 400;\">) (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 clk,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 rst_n,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic [WIDTH-1:0] count<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Now the same functional RTL can support different widths.<\/span><\/p><p><span style=\"font-weight: 400;\">Parameters are particularly useful for:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data width<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address width<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFO depth<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Counter width<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Number of channels<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Buffer size<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Parameterized RTL is also a commonly used industry pattern because it reduces duplicated modules and supports reusable IP.<\/span><\/p><h3><span style=\"font-weight: 400;\">9. Avoid Hardcoding Technology-Specific Cells in Generic RTL<\/span><\/h3><p><span style=\"font-weight: 400;\">Suppose an RTL block requires a multiplexer.<\/span><\/p><p><span style=\"font-weight: 400;\">A technology-independent implementation might be:<\/span><\/p><p><span style=\"font-weight: 400;\">assign y = sel ? b : a;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The synthesis tool can map this function to the appropriate cells available in the target library.<\/span><\/p><p><span style=\"font-weight: 400;\">Direct library-cell instantiation may instead look like:<\/span><\/p><p><span style=\"font-weight: 400;\">MYTECH_MUX2 u_mux (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0.A(a),<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0.B(b),<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0.S(sel),<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0.Y(y)<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The second approach may be necessary in some specialized situations, but it is no longer technology-agnostic.<\/span><\/p><p><span style=\"font-weight: 400;\">If a specific library cell is required for:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clocking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">I\/O<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Analog interaction<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Specialized timing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Low-power implementation<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">keep that technology-specific logic isolated from the reusable functional RTL wherever possible.<\/span><\/p><p><span style=\"font-weight: 400;\">This creates a useful separation:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Generic RTL<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0&#8212;&#8212;&#8212;&#8212;&#8212;&#8211;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0| \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0Functional\u00a0 \u00a0 \u00a0 \u00a0 Technology-<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Logic\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Specific Layer<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This approach improves portability and makes later technology migration easier.<\/span><\/p><h3><span style=\"font-weight: 400;\">10. Do Not Manually Build Clock Gating Without Understanding the Flow<\/span><\/h3><p><span style=\"font-weight: 400;\">Clock logic requires special care.<\/span><\/p><p><span style=\"font-weight: 400;\">A beginner might write:<\/span><\/p><p><span style=\"font-weight: 400;\">assign gated_clk = clk &amp; enable;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This appears simple, but it creates a derived clock and can introduce clock skew, glitches and implementation problems.<\/span><\/p><p><span style=\"font-weight: 400;\">For ASIC flows, dedicated integrated clock-gating cells are commonly used rather than treating an ordinary combinational AND gate as a generic clock-gating solution.<\/span><\/p><p><span style=\"font-weight: 400;\">The exact methodology depends on the technology and implementation flow.<\/span><\/p><p><span style=\"font-weight: 400;\">For reusable RTL, a clock-enable structure is often preferable when the requirement is simply to prevent unnecessary register updates:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This keeps the clock itself unchanged while controlling when the register captures new data.<\/span><\/p><p><span style=\"font-weight: 400;\">Inskill&#8217;s existing RTL coding-pattern material also discusses clock-enable structures as a common RTL pattern.<\/span><\/p><h3><span style=\"font-weight: 400;\">11. Keep Reset Intent Clear<\/span><\/h3><p><span style=\"font-weight: 400;\">Reset logic affects synthesis, timing, verification and physical implementation.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk or negedge rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This describes an asynchronously reset register.<\/span><\/p><p><span style=\"font-weight: 400;\">A synchronous reset would instead be:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Neither approach should automatically be treated as universally better.<\/span><\/p><p><span style=\"font-weight: 400;\">The correct choice depends on the design architecture and project requirements.<\/span><\/p><p><span style=\"font-weight: 400;\">The important principle is:<\/span><\/p><p><span style=\"font-weight: 400;\">Do not hide reset behavior in complicated logic. Make the reset strategy obvious and consistent.<\/span><\/p><h3><span style=\"font-weight: 400;\">12. Write FSMs With Clear State and Transition Logic<\/span><\/h3><p><span style=\"font-weight: 400;\">Finite-state machines are common in RTL.<\/span><\/p><p><span style=\"font-weight: 400;\">A clean structure separates state storage from next-state logic.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">typedef enum logic [1:0] {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0IDLE,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0START,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0ACTIVE,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0DONE<\/span><\/p><p><span style=\"font-weight: 400;\">} state_t;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">state_t state, next_state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">State register:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk or negedge rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0state &lt;= IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0state &lt;= next_state;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Next-state logic:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0next_state = state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (state)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0IDLE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (start)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = START;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0START: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = ACTIVE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0ACTIVE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (done)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = DONE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0DONE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This structure makes the state machine easier to review and verify.<\/span><\/p><p><span style=\"font-weight: 400;\">It also helps prevent incomplete assignments and unintended latch inference.<\/span><\/p><h3><span style=\"font-weight: 400;\">13. Use <\/span><span style=\"font-weight: 400;\">case<\/span><span style=\"font-weight: 400;\"> Carefully<\/span><\/h3><p><span style=\"font-weight: 400;\">Incomplete or ambiguous case logic can cause problems.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b00: y = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: y = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">What happens when <\/span><span style=\"font-weight: 400;\">sel<\/span><span style=\"font-weight: 400;\"> is <\/span><span style=\"font-weight: 400;\">2&#8217;b10<\/span><span style=\"font-weight: 400;\"> or <\/span><span style=\"font-weight: 400;\">2&#8217;b11<\/span><span style=\"font-weight: 400;\">?<\/span><\/p><p><span style=\"font-weight: 400;\">If <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\"> has no defined value for those conditions, the intended hardware may not be what the designer expects.<\/span><\/p><p><span style=\"font-weight: 400;\">A safer pattern is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = &#8216;0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b00: y = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: y = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b10: y = c;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b11: y = d;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default: y = &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The appropriate use of <\/span><span style=\"font-weight: 400;\">unique<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">priority<\/span><span style=\"font-weight: 400;\">, or other SystemVerilog constructs should follow the project&#8217;s coding and verification methodology rather than being added automatically.<\/span><\/p><h3><span style=\"font-weight: 400;\">14. Avoid Multiple Drivers for the Same Signal<\/span><\/h3><p><span style=\"font-weight: 400;\">A signal should normally have one clear source of procedural assignment.<\/span><\/p><p><span style=\"font-weight: 400;\">Avoid structures such as:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q &lt;= a;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q &lt;= b;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This creates multiple procedural drivers for <\/span><span style=\"font-weight: 400;\">q<\/span><span style=\"font-weight: 400;\"> and is not the intended description of an ordinary register.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead, combine the control:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Clear ownership makes RTL easier for synthesis, lint and human reviewers to understand.<\/span><\/p><h3><span style=\"font-weight: 400;\">15. Be Careful With Combinational Depth<\/span><\/h3><p><span style=\"font-weight: 400;\">Synthesis-friendly RTL is not just about whether the code synthesizes.<\/span><\/p><p><span style=\"font-weight: 400;\">The resulting hardware also needs to meet timing.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider a long chain of combinational operations:<\/span><\/p><p><span style=\"font-weight: 400;\">Input<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Register<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A long combinational path can make timing closure difficult.<\/span><\/p><p><span style=\"font-weight: 400;\">One solution is pipelining:<\/span><\/p><p><span style=\"font-weight: 400;\">Input<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Register<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Logic<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Register<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">Output<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Pipelining changes latency, so it cannot simply be inserted without considering the functional specification.<\/span><\/p><p><span style=\"font-weight: 400;\">The important point is that RTL structure influences the eventual timing architecture.<\/span><\/p><p><span style=\"font-weight: 400;\">Current RTL guidance similarly emphasizes coding structures that help synthesis produce efficient implementations and meet timing objectives.<\/span><\/p><h3><span style=\"font-weight: 400;\">16. Do Not Assume Synthesis Will Fix Poor RTL Structure<\/span><\/h3><p><span style=\"font-weight: 400;\">Synthesis tools perform extensive optimization, but they cannot infer design intent that was never correctly expressed.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if RTL accidentally creates:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A latch<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An unintended priority chain<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A very deep combinational path<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A wrong-width arithmetic operation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A combinational feedback loop<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An incorrect clock relationship<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">the designer should not rely on synthesis to automatically repair the problem.<\/span><\/p><p><span style=\"font-weight: 400;\">A better principle is:<\/span><\/p><p><span style=\"font-weight: 400;\">Write correct hardware intent first; use synthesis to optimize the intended hardware.<\/span><\/p><h3><span style=\"font-weight: 400;\">17. Separate Functional RTL From Technology-Specific Implementation<\/span><\/h3><p><span style=\"font-weight: 400;\">A scalable SoC project often has multiple abstraction levels.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Reusable IP<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Technology-Independent RTL<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Synthesis<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Technology Mapping<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0|<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0v<\/span><\/p><p><span style=\"font-weight: 400;\">Standard Cells \/ Memories \/ Macros<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Technology-specific elements can then be handled separately.<\/span><\/p><p><span style=\"font-weight: 400;\">Examples include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Standard-cell libraries<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory macros<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">I\/O cells<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock cells<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Physical-only cells<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Technology-specific power cells<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This separation makes the functional RTL easier to reuse.<\/span><\/p><p><span style=\"font-weight: 400;\">It also allows the implementation team to change the target library without rewriting the entire functional design.<\/span><\/p><h3><span style=\"font-weight: 400;\">18. Understand What &#8220;Technology-Agnostic&#8221; Does Not Mean<\/span><\/h3><p><span style=\"font-weight: 400;\">Technology-agnostic does <\/span><b>not<\/b><span style=\"font-weight: 400;\"> mean that the RTL will produce exactly the same hardware in every technology.<\/span><\/p><p><span style=\"font-weight: 400;\">Different libraries have different:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Cell architectures<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Drive strengths<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Threshold-voltage options<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory macros<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Timing characteristics<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power characteristics<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The synthesis tool will map the same functional RTL differently depending on the target technology and constraints.<\/span><\/p><p><span style=\"font-weight: 400;\">Technology independence means the <\/span><b>functional description<\/b><span style=\"font-weight: 400;\"> does not unnecessarily depend on a particular implementation technology.<\/span><\/p><h3><span style=\"font-weight: 400;\">19. Use Lint Before Synthesis<\/span><\/h3><p><span style=\"font-weight: 400;\">Lint is one of the most useful ways to catch RTL problems early.<\/span><\/p><p><span style=\"font-weight: 400;\">A lint tool can identify issues such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Inferred latches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Width mismatches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Undriven signals<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiple drivers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unreachable logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Suspicious case statements<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock\/reset issues<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Coding-style violations<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The earlier these issues are found, the cheaper they are to fix.<\/span><\/p><p><span style=\"font-weight: 400;\">A practical RTL flow is:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL Coding<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Lint<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Simulation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Synthesis<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">STA<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Implementation<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Do not wait for synthesis to discover basic coding problems.<\/span><\/p><h3><span style=\"font-weight: 400;\">20. Compare Simulation and Synthesis Results<\/span><\/h3><p><span style=\"font-weight: 400;\">A design can behave differently in simulation and after synthesis if the RTL contains ambiguous or unsupported behavior.<\/span><\/p><p><span style=\"font-weight: 400;\">Common causes include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incomplete combinational assignments<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect sensitivity lists<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Blocking\/non-blocking misuse<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unsized constants<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Signedness errors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Initialization assumptions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Simulation-only constructs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Race conditions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect reset assumptions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The goal is to minimize the possibility of <\/span><b>simulation-synthesis mismatches<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">A strong RTL engineer therefore thinks about both:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;What does the simulator do?&#8221;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;What hardware will this code actually infer?&#8221;<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">21. Write RTL With Verification in Mind<\/span><\/h3><p><span style=\"font-weight: 400;\">Synthesis-friendly RTL should also be verification-friendly.<\/span><\/p><p><span style=\"font-weight: 400;\">Clear interfaces and predictable behavior make it easier to create:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Functional coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Monitors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Formal properties<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Debug waveforms<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example, if a valid-ready interface is clearly defined:<\/span><\/p><p><span style=\"font-weight: 400;\">assign transfer = valid &amp;&amp; ready;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the verification environment has an obvious transaction condition to check.<\/span><\/p><p><span style=\"font-weight: 400;\">Inskill&#8217;s existing RTL coding guidance similarly emphasizes verification-friendly RTL as part of practical industry design.<\/span><\/p><h3><span style=\"font-weight: 400;\">22. Avoid Over-Optimization at the RTL Stage<\/span><\/h3><p><span style=\"font-weight: 400;\">A common mistake is trying to manually optimize every gate.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a designer may rewrite simple Boolean logic specifically to force a particular gate arrangement.<\/span><\/p><p><span style=\"font-weight: 400;\">That can make the RTL:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Harder to understand<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Less reusable<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">More technology-dependent<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">More difficult to verify<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">If there is no architectural reason to control the exact implementation, describe the intended behavior clearly and allow synthesis to optimize it.<\/span><\/p><p><span style=\"font-weight: 400;\">RTL optimization is valuable when it addresses a real requirement such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Timing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Area<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Resource sharing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Pipeline structure<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">But optimization should be driven by measurable design requirements rather than assumptions about what the synthesis tool will produce.<\/span><\/p><h3><span style=\"font-weight: 400;\">A Practical Example<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider this simple combinational block.<\/span><\/p><h5><span style=\"font-weight: 400;\">Less robust version<\/span><\/h5><p><span style=\"font-weight: 400;\">always @(*) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = a + b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The problem is that <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\"> is not assigned when <\/span><span style=\"font-weight: 400;\">enable<\/span><span style=\"font-weight: 400;\"> is false.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better version<\/span><\/h5><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0y = &#8216;0;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = a + b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Now the intended behavior is clear:<\/span><\/p><p><span style=\"font-weight: 400;\">enable = 1 \u2192 y = a + b<\/span><\/p><p><span style=\"font-weight: 400;\">enable = 0 \u2192 y = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">And the combinational block has a defined output for both conditions.<\/span><\/p><h5><span style=\"font-weight: 400;\">Another Example: Reusable RTL<\/span><\/h5><p><span style=\"font-weight: 400;\">Instead of:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] counter;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">use:<\/span><\/p><p><span style=\"font-weight: 400;\">module counter #(<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0parameter int WIDTH = 8<\/span><\/p><p><span style=\"font-weight: 400;\">) (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 clk,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 rst_n,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 enable,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic [WIDTH-1:0] count<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk or negedge rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0count &lt;= &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0count &lt;= count + 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endmodule<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The same module can support:<\/span><\/p><p><span style=\"font-weight: 400;\">WIDTH = 8<\/span><\/p><p><span style=\"font-weight: 400;\">WIDTH = 16<\/span><\/p><p><span style=\"font-weight: 400;\">WIDTH = 32<\/span><\/p><p><span style=\"font-weight: 400;\">WIDTH = 64<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">without rewriting the functional design.<\/span><\/p><p><span style=\"font-weight: 400;\">That is an example of both <\/span><b>synthesis-friendly<\/b><span style=\"font-weight: 400;\"> and <\/span><b>reusable<\/b><span style=\"font-weight: 400;\"> RTL.<\/span><\/p><h3><span style=\"font-weight: 400;\">Technology-Agnostic RTL Checklist<\/span><\/h3><p><span style=\"font-weight: 400;\">Before submitting an RTL block for synthesis, ask:<\/span><\/p><h5><span style=\"font-weight: 400;\">Functional correctness<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does the RTL implement the specification?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are all state transitions defined?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are reset conditions clear?<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Synthesis<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are all constructs supported by the intended synthesis flow?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are there unintended latches?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are there multiple drivers?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are combinational paths complete?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are clocked assignments using the project&#8217;s required style?<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Portability<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does the RTL unnecessarily instantiate technology-specific cells?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are technology-specific elements isolated?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are widths and types explicitly defined?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are parameters used where reuse is expected?<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Timing<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are there unnecessarily deep combinational paths?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are pipeline stages required?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are clock relationships clearly defined?<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Verification<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Is the RTL easy to observe and debug?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can important behavior be asserted?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are interfaces and transaction boundaries clear?<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Maintainability<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are names meaningful?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Is the module reasonably sized?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Are repeated structures parameterized?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can another engineer understand the hardware intent quickly?<\/span><\/li><\/ul><p>\u00a0<\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">Making RTL synthesis-friendly does not mean memorizing a list of forbidden Verilog statements.<\/span><\/p><p><span style=\"font-weight: 400;\">It means developing the habit of asking:<\/span><\/p><p><span style=\"font-weight: 400;\">What hardware does this RTL describe?<\/span><\/p><p><span style=\"font-weight: 400;\">And for technology independence:<\/span><\/p><p><span style=\"font-weight: 400;\">Does this RTL describe the required function, or am I unnecessarily describing a particular implementation technology?<\/span><\/p><p><span style=\"font-weight: 400;\">Good RTL should:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clearly express hardware intent<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Avoid unintended latches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Separate combinational and sequential behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Use appropriate assignment styles<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Make widths and signedness explicit<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Use parameters for reusable structures<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Keep clock and reset behavior clear<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Avoid unnecessary technology-specific cells<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Consider timing and power implications<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Work well with lint, simulation and synthesis<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Remain understandable to verification and implementation engineers<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The objective is not to force the synthesis tool to produce a particular set of gates. The objective is to provide a <\/span><b>correct, clear and reusable hardware description<\/b><span style=\"font-weight: 400;\"> that synthesis can map efficiently to the target technology.<\/span><\/p><p><span style=\"font-weight: 400;\">That is the foundation of professional RTL design.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Writing RTL that produces the expected simulation result is only one part of digital design. For an RTL design to be useful in an ASIC or SoC development flow, it must also describe hardware clearly enough for synthesis tools to convert it into the intended gate-level implementation. At the same time, reusable RTL should avoid [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10195","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>How to Write Synthesis-Friendly and Technology-Agnostic RTL<\/title>\n<meta name=\"description\" content=\"Learn how to write synthesis-friendly, technology-agnostic RTL with practical Verilog and SystemVerilog coding guidelines for ASIC design.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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