{"id":10210,"date":"2026-09-25T08:47:18","date_gmt":"2026-09-25T08:47:18","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10210"},"modified":"2026-09-22T08:49:25","modified_gmt":"2026-09-22T08:49:25","slug":"common-axi-design-mistakes","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/common-axi-design-mistakes\/","title":{"rendered":"Common AXI Design Mistakes and How to Avoid Them"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10210\" class=\"elementor elementor-10210\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-9325cb2 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"9325cb2\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-9212e26\" data-id=\"9212e26\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-860b3fd elementor-widget elementor-widget-text-editor\" data-id=\"860b3fd\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">AXI is widely used for communication between IP blocks in modern SoCs, but implementing an AXI interface correctly is more than connecting the right signals.<\/span><\/p><p><span style=\"font-weight: 400;\">Many AXI problems come from relatively small RTL design decisions: making <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> depend incorrectly on <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\">, losing information when backpressure occurs, mishandling burst boundaries, assuming read and write channels always progress together, or failing to account for multiple outstanding transactions.<\/span><\/p><p><span style=\"font-weight: 400;\">These issues can be particularly difficult to debug because an AXI interface may work perfectly in a simple simulation and fail when the slave applies backpressure, transactions overlap, or a burst reaches an address boundary.<\/span><\/p><p><span style=\"font-weight: 400;\">This guide explains the common AXI design mistakes VLSI engineers encounter in RTL, why they happen, how to avoid them, and what to check during simulation and verification.<\/span><\/p><p><span style=\"font-weight: 400;\">The examples focus on AXI4 concepts, but many of the underlying lessons apply to other ready\/valid-based interfaces as well.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Makes AXI Design Different?<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI is not a simple single-channel bus.<\/span><\/p><p><span style=\"font-weight: 400;\">AXI4 separates communication into five independent channels:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Write Address \u2014 <\/span><span style=\"font-weight: 400;\">AW<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Write Data \u2014 <\/span><span style=\"font-weight: 400;\">W<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Write Response \u2014 <\/span><span style=\"font-weight: 400;\">B<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Read Address \u2014 <\/span><span style=\"font-weight: 400;\">AR<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Read Data \u2014 <\/span><span style=\"font-weight: 400;\">R<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Each channel has its own <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> handshake.<\/span><\/p><p><span style=\"font-weight: 400;\">A transfer occurs when both sides of the handshake are asserted at the active clock edge:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID &amp;&amp; READY<\/span><\/p><p><span style=\"font-weight: 400;\">This means an AXI design has to handle not only the data itself, but also when that data is accepted, when it must remain stable, how transactions are associated, and what happens when the receiving side is not ready. Arm&#8217;s AXI documentation defines the channel structure and transaction rules in detail.<\/span><\/p><p><span style=\"font-weight: 400;\">That is where many implementation mistakes begin.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">1. Making VALID Depend on READY<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the most common mistakes is designing the source so that it waits for <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> before asserting <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">if (READY)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0VALID = 1;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This may appear convenient, but it creates an undesirable dependency between the sender and receiver.<\/span><\/p><p><span style=\"font-weight: 400;\">A source should be able to indicate that it has a valid transfer without waiting for the destination to assert <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">If both sides wait for each other, the interface can stop making progress.<\/span><\/p><p><span style=\"font-weight: 400;\">A ready\/valid interface is intended to allow the source to assert <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> when data is available while the destination independently controls <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Think of the signals this way:<\/span><\/p><p><b>Source controls:<\/b><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Payload<\/span><\/li><\/ul><p><b>Destination controls:<\/b><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">READY<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The source says:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;I have something to transfer.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">The destination says:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;I can accept it.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">The transfer happens when:<\/span><\/p><p><b>VALID = 1 AND READY = 1<\/b><\/p><p><span style=\"font-weight: 400;\">This principle should be applied independently to each AXI channel.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">2. Changing Payload While VALID Is High and READY Is Low<\/span><\/h3><p><span style=\"font-weight: 400;\">Another common error occurs when the source changes the address, data, or control information while <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> is asserted but <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> is low.<\/span><\/p><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">Cycle 1:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p><span style=\"font-weight: 400;\">DATA = A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Cycle 2:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p><span style=\"font-weight: 400;\">DATA = B<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The receiver has not accepted the first transfer.<\/span><\/p><p><span style=\"font-weight: 400;\">Changing the payload without a valid transfer can therefore violate the intended handshake behavior.<\/span><\/p><h5><span style=\"font-weight: 400;\">Correct approach<\/span><\/h5><p><span style=\"font-weight: 400;\">Once the source asserts <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\">, it should keep the relevant transfer information stable until the handshake occurs.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p><span style=\"font-weight: 400;\">DATA = A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p><span style=\"font-weight: 400;\">DATA = A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p><span style=\"font-weight: 400;\">DATA = A<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The transfer happens on the final cycle.<\/span><\/p><p><span style=\"font-weight: 400;\">This is one of the first waveform checks you should perform when debugging an AXI interface.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">3. Treating the Five AXI Channels as One Transaction<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI has independent channels.<\/span><\/p><p><span style=\"font-weight: 400;\">A common design mistake is assuming that the write address and write data must always arrive together.<\/span><\/p><p><span style=\"font-weight: 400;\">They do not have to behave as a single combined channel.<\/span><\/p><p><span style=\"font-weight: 400;\">For writes, AXI separates:<\/span><\/p><p><b>Write Address \u2192 AW channel<\/b><\/p><p><span style=\"font-weight: 400;\">from<\/span><\/p><p><b>Write Data \u2192 W channel<\/b><\/p><p><span style=\"font-weight: 400;\">and the completion response uses:<\/span><\/p><p><b>Write Response \u2192 B channel<\/b><\/p><p><span style=\"font-weight: 400;\">This means an RTL implementation must be able to handle legal differences in timing between these channels.<\/span><\/p><h5><span style=\"font-weight: 400;\">Why this matters<\/span><\/h5><p><span style=\"font-weight: 400;\">Suppose the write address arrives first but the data arrives several cycles later.<\/span><\/p><p><span style=\"font-weight: 400;\">Your slave must be able to retain the required information and associate the pieces correctly.<\/span><\/p><p><span style=\"font-weight: 400;\">A design that assumes:<\/span><\/p><p><span style=\"font-weight: 400;\">AWVALID &amp;&amp; WVALID<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">must always occur together can work in a simple testbench and fail with a more realistic master.<\/span><\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Design and verify each channel according to its own handshake rules.<\/span><\/p><p><span style=\"font-weight: 400;\">Then explicitly handle the relationships between channels where the protocol requires them.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">4. Forgetting Backpressure<\/span><\/h3><p><span style=\"font-weight: 400;\">Backpressure is normal in AXI.<\/span><\/p><p><span style=\"font-weight: 400;\">A slave may temporarily deassert <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> because:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Internal storage is full<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A pipeline is busy<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A downstream block is stalled<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A response queue is full<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Arbitration is delaying the transaction<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A common mistake is testing an interface only when:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">all the time.<\/span><\/p><p><span style=\"font-weight: 400;\">That does not adequately test the handshake logic.<\/span><\/p><p><span style=\"font-weight: 400;\">Arm&#8217;s current AXI learning material emphasizes understanding how transactions behave in real systems, including data flow, correctness and performance.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better verification<\/span><\/h5><p><span style=\"font-weight: 400;\">Randomly or deliberately introduce periods where:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Then verify that:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> remains asserted as required<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Payload remains stable<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">No transfer is lost<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">No transfer is duplicated<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The interface eventually resumes<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Backpressure testing is one of the simplest ways to expose weak AXI RTL.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">5. Assuming READY Must Always Be High<\/span><\/h3><p><span style=\"font-weight: 400;\">The opposite mistake is designing or verifying an AXI interface under the assumption that <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> is permanently asserted.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">assign ARREADY = 1&#8217;b1;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">may be valid for a very simple interface if the architecture genuinely supports accepting every request immediately.<\/span><\/p><p><span style=\"font-weight: 400;\">But a more realistic slave may need to apply backpressure.<\/span><\/p><p><span style=\"font-weight: 400;\">If the RTL cannot tolerate <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> going low, it has not been tested against an important part of the protocol behavior.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better approach<\/span><\/h5><p><span style=\"font-weight: 400;\">Design the interface so that it works correctly when:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and when:<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">for multiple cycles.<\/span><\/p><p><span style=\"font-weight: 400;\">Then verify both cases.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">6. Creating Combinational Loops Between VALID and READY<\/span><\/h3><p><span style=\"font-weight: 400;\">A subtle but important problem occurs when the source&#8217;s <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> depends on the destination&#8217;s <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\">, while the destination&#8217;s <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> depends on the source&#8217;s <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Master VALID \u2192 Slave READY<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2191\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2193<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This can create a combinational loop.<\/span><\/p><p><span style=\"font-weight: 400;\">Ready\/valid interfaces are particularly vulnerable to this type of design problem because both signals control whether a transfer occurs.<\/span><\/p><p><span style=\"font-weight: 400;\">A common solution is to derive the control from registered state or otherwise ensure that the interface does not create an unintended combinational path between source and destination.<\/span><\/p><h5><span style=\"font-weight: 400;\">Practical check<\/span><\/h5><p><span style=\"font-weight: 400;\">When reviewing an AXI interface, ask:<\/span><\/p><p><b>Can <\/b><b>VALID<\/b><b> change combinationally because of <\/b><b>READY<\/b><b>?<\/b><\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><b>Can <\/b><b>READY<\/b><b> change combinationally because of <\/b><b>VALID<\/b><b>?<\/b><\/p><p><span style=\"font-weight: 400;\">If the answer produces a loop across connected IP blocks, the architecture needs to be reconsidered.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">7. Mishandling AXI Burst Length<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI is burst-based, so burst parameters need careful handling.<\/span><\/p><p><span style=\"font-weight: 400;\">Important fields include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AxLEN<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AxSIZE<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AxBURST<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AxADDR<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The AXI specification defines the burst length and size rules, and AXI4 allows INCR bursts of up to 256 transfers.<\/span><\/p><p><span style=\"font-weight: 400;\">A common RTL mistake is interpreting <\/span><span style=\"font-weight: 400;\">AxLEN<\/span><span style=\"font-weight: 400;\"> directly as the number of transfers.<\/span><\/p><p><span style=\"font-weight: 400;\">For AXI4:<\/span><\/p><p><b>Burst length = AxLEN + 1<\/b><\/p><p><span style=\"font-weight: 400;\">So:<\/span><\/p><p><span style=\"font-weight: 400;\">AxLEN = 0 \u2192 1 transfer<\/span><\/p><p><span style=\"font-weight: 400;\">AxLEN = 3 \u2192 4 transfers<\/span><\/p><p><span style=\"font-weight: 400;\">AxLEN = 7 \u2192 8 transfers<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Create a clearly defined internal representation such as:<\/span><\/p><p><span style=\"font-weight: 400;\">beats_remaining = AxLEN + 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and decrement it only when an actual data transfer occurs.<\/span><\/p><p><span style=\"font-weight: 400;\">This makes the RTL and verification environment easier to reason about.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">8. Ignoring the 4 KB Burst Boundary Rule<\/span><\/h3><p><span style=\"font-weight: 400;\">This is a particularly important AXI design error.<\/span><\/p><p><span style=\"font-weight: 400;\">An AXI burst must not cross a <\/span><b>4 KB address boundary<\/b><span style=\"font-weight: 400;\">. The rule exists in part to prevent a burst from crossing between different slaves and to limit the address range a subordinate needs to handle.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a burst beginning near the end of one 4 KB region may need to be split rather than allowed to continue into the next region.<\/span><\/p><h5><span style=\"font-weight: 400;\">Why this matters<\/span><\/h5><p><span style=\"font-weight: 400;\">If an address generator simply calculates:<\/span><\/p><p><span style=\"font-weight: 400;\">next_address = current_address + transfer_size;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">without checking the boundary, it can generate an illegal burst.<\/span><\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Before issuing a burst, calculate:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Start address<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Number of beats<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Bytes per beat<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Final address<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Then verify that the burst remains within the same 4 KB region.<\/span><\/p><p><span style=\"font-weight: 400;\">This check belongs in the design or transaction-generation logic where appropriate, rather than relying only on the testbench to catch it.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">9. Getting Burst Address Calculation Wrong<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI supports different burst types.<\/span><\/p><p><span style=\"font-weight: 400;\">The main types are:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIXED<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">INCR<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">WRAP<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">An <\/span><span style=\"font-weight: 400;\">INCR<\/span><span style=\"font-weight: 400;\"> burst increments the address according to the transfer size.<\/span><\/p><p><span style=\"font-weight: 400;\">A <\/span><span style=\"font-weight: 400;\">FIXED<\/span><span style=\"font-weight: 400;\"> burst keeps the address constant.<\/span><\/p><p><span style=\"font-weight: 400;\">A <\/span><span style=\"font-weight: 400;\">WRAP<\/span><span style=\"font-weight: 400;\"> burst follows wrapping-address rules.<\/span><\/p><p><span style=\"font-weight: 400;\">The AXI specification defines these behaviors explicitly.<\/span><\/p><h5><span style=\"font-weight: 400;\">Common mistake<\/span><\/h5><p><span style=\"font-weight: 400;\">Designers sometimes assume every burst behaves like:<\/span><\/p><p><span style=\"font-weight: 400;\">address = address + data_width<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">That is not generally correct.<\/span><\/p><p><span style=\"font-weight: 400;\">The address increment is determined by the transfer size, not simply by the physical width of the bus.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better approach<\/span><\/h5><p><span style=\"font-weight: 400;\">Calculate the number of bytes per beat from <\/span><span style=\"font-weight: 400;\">AxSIZE<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">bytes_per_beat = 2 ^ AxSIZE<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Then use the correct address-generation algorithm for the selected burst type.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">10. Ignoring WSTRB During AXI Writes<\/span><\/h3><p><span style=\"font-weight: 400;\">WSTRB<\/span><span style=\"font-weight: 400;\"> identifies which byte lanes of write data are valid.<\/span><\/p><p><span style=\"font-weight: 400;\">A slave should not simply assume that every byte of <\/span><span style=\"font-weight: 400;\">WDATA<\/span><span style=\"font-weight: 400;\"> is meaningful on every transfer.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, on a 32-bit data bus:<\/span><\/p><p><span style=\"font-weight: 400;\">WDATA\u00a0 = 32 bits<\/span><\/p><p><span style=\"font-weight: 400;\">WSTRB\u00a0 = 4 bits<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Each strobe bit corresponds to a byte lane.<\/span><\/p><p><span style=\"font-weight: 400;\">Conceptually:<\/span><\/p><p><span style=\"font-weight: 400;\">WSTRB[0] \u2192 byte 0<\/span><\/p><p><span style=\"font-weight: 400;\">WSTRB[1] \u2192 byte 1<\/span><\/p><p><span style=\"font-weight: 400;\">WSTRB[2] \u2192 byte 2<\/span><\/p><p><span style=\"font-weight: 400;\">WSTRB[3] \u2192 byte 3<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If only some strobes are asserted, the design must preserve the unaffected bytes according to the memory\/register semantics.<\/span><\/p><h5><span style=\"font-weight: 400;\">Common failure<\/span><\/h5><p><span style=\"font-weight: 400;\">A register or memory implementation writes all 32 bits regardless of <\/span><span style=\"font-weight: 400;\">WSTRB<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">That can silently corrupt existing data during partial writes.<\/span><\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Make byte-enable behavior explicit in the RTL and include partial-write cases in the testbench.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">11. Mishandling the Last Beat of a Burst<\/span><\/h3><p><span style=\"font-weight: 400;\">For AXI write and read data channels, the <\/span><span style=\"font-weight: 400;\">LAST<\/span><span style=\"font-weight: 400;\"> signal identifies the final data transfer of a burst.<\/span><\/p><p><span style=\"font-weight: 400;\">A common mistake is generating <\/span><span style=\"font-weight: 400;\">LAST<\/span><span style=\"font-weight: 400;\"> based on a cycle counter rather than on <\/span><b>actual accepted transfers<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if:<\/span><\/p><p><span style=\"font-weight: 400;\">WVALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">WREADY = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">the write data has not transferred.<\/span><\/p><p><span style=\"font-weight: 400;\">The burst counter should not advance simply because a clock cycle passed.<\/span><\/p><h5><span style=\"font-weight: 400;\">Correct principle<\/span><\/h5><p><span style=\"font-weight: 400;\">Update transaction state when the handshake occurs:<\/span><\/p><p><span style=\"font-weight: 400;\">WVALID &amp;&amp; WREADY<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">not merely because:<\/span><\/p><p><span style=\"font-weight: 400;\">WVALID<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">is high.<\/span><\/p><p><span style=\"font-weight: 400;\">This distinction is critical when backpressure is present.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">12. Advancing State Without a Handshake<\/span><\/h3><p><span style=\"font-weight: 400;\">This mistake appears in many AXI implementations.<\/span><\/p><p><span style=\"font-weight: 400;\">Suppose an RTL block does:<\/span><\/p><p><span style=\"font-weight: 400;\">if (VALID)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0counter &lt;= counter + 1;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">But the actual transfer occurs only when:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID &amp;&amp; READY<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The counter can therefore move ahead of the transaction.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better pattern<\/span><\/h5><p><span style=\"font-weight: 400;\">For a channel where transfer completion is defined by the handshake:<\/span><\/p><p><span style=\"font-weight: 400;\">if (VALID &amp;&amp; READY)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0update_transaction_state();<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This applies to:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Counters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Burst tracking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address updates<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFO pointers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Beat counters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Transaction completion flags<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The important question is always:<\/span><\/p><p><b>Did the transfer actually happen?<\/b><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">13. Incorrect Reset Behavior<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI interfaces contain many state-holding elements.<\/span><\/p><p><span style=\"font-weight: 400;\">Reset may affect:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Valid signals<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Ready logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Transaction counters<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Burst tracking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Outstanding transaction state<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Response generation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Internal FIFOs<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A common mistake is resetting only the visible AXI signals while leaving internal transaction state inconsistent.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, the interface may come out of reset with:<\/span><\/p><p><span style=\"font-weight: 400;\">AWVALID = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">but an internal state machine still believes a write transaction is active.<\/span><\/p><p><span style=\"font-weight: 400;\">That can produce difficult-to-debug failures later.<\/span><\/p><h5><span style=\"font-weight: 400;\">Better approach<\/span><\/h5><p><span style=\"font-weight: 400;\">For every AXI channel, document:<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset value<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">State after reset<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Conditions for becoming active<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Conditions for completing a transaction<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">Then verify reset both during initialization and in appropriate reset\/recovery scenarios.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">14. Mishandling Read and Write Responses<\/span><\/h3><p><span style=\"font-weight: 400;\">A slave should generate responses based on completed transactions, not merely because a request was observed.<\/span><\/p><p><span style=\"font-weight: 400;\">For writes, the <\/span><span style=\"font-weight: 400;\">B<\/span><span style=\"font-weight: 400;\"> channel carries the write response.<\/span><\/p><p><span style=\"font-weight: 400;\">For reads, the <\/span><span style=\"font-weight: 400;\">R<\/span><span style=\"font-weight: 400;\"> channel carries read data and response information.<\/span><\/p><p><span style=\"font-weight: 400;\">A common design error is generating a response too early or losing the relationship between the response and the transaction that caused it.<\/span><\/p><p><span style=\"font-weight: 400;\">This becomes more complicated when multiple transactions can be outstanding.<\/span><\/p><h5><span style=\"font-weight: 400;\">What to check<\/span><\/h5><p><span style=\"font-weight: 400;\">For every transaction, verify:<\/span><\/p><p><b>Request \u2192 Processing \u2192 Response<\/b><\/p><p><span style=\"font-weight: 400;\">and ensure that:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The response is generated exactly once<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The response corresponds to the correct transaction<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error conditions are represented correctly<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Response backpressure is handled<\/span><\/li><\/ul><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">15. Ignoring Multiple Outstanding Transactions<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI can support multiple transactions in flight.<\/span><\/p><p><span style=\"font-weight: 400;\">This is useful for performance, but it introduces additional design complexity.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a master may issue several read requests before receiving all the read data.<\/span><\/p><p><span style=\"font-weight: 400;\">If the design assumes:<\/span><\/p><p><span style=\"font-weight: 400;\">one request \u2192 one response \u2192 next request<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">it may accidentally create a much more restrictive interface than intended or mishandle legal transaction behavior.<\/span><\/p><p><span style=\"font-weight: 400;\">Arm&#8217;s AXI material discusses outstanding transactions and the role they play in system performance and traffic management.<\/span><\/p><h5><span style=\"font-weight: 400;\">How to avoid it<\/span><\/h5><p><span style=\"font-weight: 400;\">Decide explicitly whether your IP supports:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">One outstanding transaction<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiple outstanding transactions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiple IDs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Specific ordering behavior<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Then make the RTL and verification environment consistent with that architectural decision.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">16. Ignoring Transaction IDs and Ordering<\/span><\/h3><p><span style=\"font-weight: 400;\">When multiple transactions are active, transaction IDs become important.<\/span><\/p><p><span style=\"font-weight: 400;\">A design that simply stores one request in one register may not be sufficient if the interface allows multiple transactions to remain outstanding.<\/span><\/p><p><span style=\"font-weight: 400;\">AXI&#8217;s ordering model contains rules around transaction IDs and ordering requirements. Arm has also published updates to the AXI specification addressing ordering and unique-ID behavior.<\/span><\/p><h5><span style=\"font-weight: 400;\">Practical rule<\/span><\/h5><p><span style=\"font-weight: 400;\">Do not implement ID handling as an afterthought.<\/span><\/p><p><span style=\"font-weight: 400;\">At the architecture stage, determine:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which IDs are accepted?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">How many transactions can be outstanding?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can responses return independently?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What ordering must be preserved?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">How are transactions tracked internally?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This is especially important for high-performance AXI masters, slaves and interconnect-related logic.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">17. Designing Only for the &#8220;Happy Path&#8221;<\/span><\/h3><p><span style=\"font-weight: 400;\">A basic test might look like:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID = 1<\/span><\/p><p><span style=\"font-weight: 400;\">READY = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">every cycle.<\/span><\/p><p><span style=\"font-weight: 400;\">Everything works.<\/span><\/p><p><span style=\"font-weight: 400;\">But real bugs often appear when the interface is stressed.<\/span><\/p><p><span style=\"font-weight: 400;\">A useful AXI testbench should introduce conditions such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Delayed <\/span><span style=\"font-weight: 400;\">READY<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Delayed <\/span><span style=\"font-weight: 400;\">VALID<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Back-to-back transfers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Single-beat transfers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Maximum-length bursts<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Partial writes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Different burst sizes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Different burst types<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset during appropriate transaction scenarios<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Response delays<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multiple outstanding transactions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The goal is not to create random complexity for its own sake.<\/span><\/p><p><span style=\"font-weight: 400;\">The goal is to test the situations in which the RTL&#8217;s assumptions are most likely to break.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">18. Not Using Assertions for Protocol Rules<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI behavior is often well suited to assertion-based verification.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of discovering every protocol violation manually from waveforms, assertions can continuously check important properties.<\/span><\/p><p><span style=\"font-weight: 400;\">Examples include checking that:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Payload remains stable while <\/span><span style=\"font-weight: 400;\">VALID<\/span><span style=\"font-weight: 400;\"> is high and <\/span><span style=\"font-weight: 400;\">READY<\/span><span style=\"font-weight: 400;\"> is low<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A burst has the expected number of beats<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">LAST<\/span><span style=\"font-weight: 400;\"> occurs on the appropriate final beat<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Internal state advances only after a handshake<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Requests eventually produce the expected response under the assumptions of the design<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Illegal combinations do not occur<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A simple ready\/valid stability property can conceptually look like:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_data_stable;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0VALID &amp;&amp; !READY |=&gt; VALID &amp;&amp; $stable(DATA);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact assertion should be adapted to the channel and protocol property being checked.<\/span><\/p><p><span style=\"font-weight: 400;\">The important point is that <\/span><b>assertions should express protocol intent<\/b><span style=\"font-weight: 400;\">, not simply duplicate implementation details.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">19. Debugging AXI Waveforms Without Looking at the Handshake First<\/span><\/h3><p><span style=\"font-weight: 400;\">AXI waveforms can contain dozens of signals.<\/span><\/p><p><span style=\"font-weight: 400;\">A common debugging mistake is looking immediately at:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Response<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">without first identifying where the handshakes occurred.<\/span><\/p><p><span style=\"font-weight: 400;\">Start with:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID<\/span><\/p><p><span style=\"font-weight: 400;\">READY<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">for the channel you are debugging.<\/span><\/p><p><span style=\"font-weight: 400;\">Then identify the exact clock edges where:<\/span><\/p><p><span style=\"font-weight: 400;\">VALID &amp;&amp; READY<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">is true.<\/span><\/p><p><span style=\"font-weight: 400;\">Only after identifying the accepted transfers should you examine:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Address<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Burst count<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ID<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Response<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">LAST<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This makes waveform debugging considerably easier.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">AXI Design Mistakes: Quick Reference<\/span><\/h3><table><tbody><tr><td><p><b>Mistake<\/b><\/p><\/td><td><p><b>Possible consequence<\/b><\/p><\/td><td><p><b>Better practice<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">VALID waits for READY<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Deadlock<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Generate VALID independently<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Payload changes while stalled<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Incorrect transfer<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Hold payload stable<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Treating channels as one<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Lost\/blocked transactions<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Handle channels independently<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Ignoring backpressure<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Data loss or deadlock<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Test READY deassertion<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">READY assumed always high<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Hidden bugs<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Stress with stalls<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Combinational VALID\/READY loop<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Timing\/functional problems<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Break dependency appropriately<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Incorrect AxLEN interpretation<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Wrong burst count<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Use AxLEN + 1<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Crossing 4 KB boundary<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Protocol violation<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Check burst boundary<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Wrong address increment<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Incorrect burst addressing<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Use AxSIZE\/AxBURST rules<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Ignoring WSTRB<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Partial-write corruption<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Implement byte enables<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Wrong LAST generation<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Broken burst termination<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Count accepted beats<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">State advances without handshake<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Lost transactions<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Update on VALID &amp; READY<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Incomplete reset state<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Post-reset failures<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Reset internal transaction state<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Poor ID handling<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Ordering errors<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Define ID\/outstanding policy<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Only happy-path testing<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Bugs escape simulation<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Add backpressure\/stress cases<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><br \/><br \/><\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">Most AXI bugs are not caused by forgetting a signal name. They come from misunderstanding when a transfer actually occurs and what the design must do when the transfer cannot occur immediately.<\/span><\/p><p><span style=\"font-weight: 400;\">The most important principles are:<\/span><\/p><ol><li><span style=\"font-weight: 400;\"> A transfer happens on a valid handshake.<\/span><\/li><li><span style=\"font-weight: 400;\"> Do not make the source unnecessarily wait for READY before asserting VALID.<\/span><\/li><li><span style=\"font-weight: 400;\"> Keep transfer information stable while waiting for acceptance.<\/span><\/li><li><span style=\"font-weight: 400;\"> Treat AXI&#8217;s channels as independent interfaces.<\/span><\/li><li><span style=\"font-weight: 400;\"> Design for backpressure rather than assuming READY is always high.<\/span><\/li><li><span style=\"font-weight: 400;\"> Handle burst length, size, type and address boundaries explicitly.<\/span><\/li><li><span style=\"font-weight: 400;\"> Update transaction state based on accepted transfers, not merely clock cycles.<\/span><\/li><li><span style=\"font-weight: 400;\"> Define outstanding transaction and ID behavior before implementing the RTL.<\/span><\/li><li><span style=\"font-weight: 400;\"> Verify the interface under stalls, bursts, partial writes and other non-ideal conditions.<\/span><\/li><li><span style=\"font-weight: 400;\"> Use assertions and waveform analysis to catch protocol errors early.<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">AXI becomes much easier to design once you stop thinking of it as a collection of signals and start thinking in terms of transactions, handshakes, state, buffering and backpressure.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, that shift in thinking is what turns AXI knowledge from interview-level theory into something useful for real RTL and SoC work.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>AXI is widely used for communication between IP blocks in modern SoCs, but implementing an AXI interface correctly is more than connecting the right signals. Many AXI problems come from relatively small RTL design decisions: making VALID depend incorrectly on READY, losing information when backpressure occurs, mishandling burst boundaries, assuming read and write channels always [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10210","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Common AXI Design Mistakes and How to Avoid Them<\/title>\n<meta name=\"description\" content=\"Learn the most common AXI design mistakes in RTL, including VALID\/READY errors, burst issues, backpressure, ordering, resets and response handling, with practical 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