{"id":10222,"date":"2026-09-29T10:09:46","date_gmt":"2026-09-29T10:09:46","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10222"},"modified":"2026-09-29T10:11:23","modified_gmt":"2026-09-29T10:11:23","slug":"functional-coverage-vs-code-coverage","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/functional-coverage-vs-code-coverage\/","title":{"rendered":"Functional Coverage vs. Code Coverage: What VLSI Engineers Should Know"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10222\" class=\"elementor elementor-10222\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-8bf2469 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"8bf2469\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-d14bc97\" data-id=\"d14bc97\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-4bb4a43 elementor-widget elementor-widget-text-editor\" data-id=\"4bb4a43\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">When engineers start <\/span><a href=\"https:\/\/inskill.in\/training\/rtl-integration-training\/\"><span style=\"font-weight: 400;\">learning RTL verification<\/span><\/a><span style=\"font-weight: 400;\">, two coverage terms appear repeatedly: <\/span><b>code coverage<\/b><span style=\"font-weight: 400;\"> and <\/span><b>functional coverage<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Both help a verification team understand how thoroughly a design has been exercised, but they answer different questions.<\/span><\/p><p><b>Code coverage asks:<\/b><\/p><p><span style=\"font-weight: 400;\">Which parts of the RTL were executed?<\/span><\/p><p><b>Functional coverage asks:<\/b><\/p><p><span style=\"font-weight: 400;\">Which features, scenarios, values, combinations, and behaviors defined as important in the verification plan were exercised?<\/span><\/p><p><span style=\"font-weight: 400;\">That distinction is important.<\/span><\/p><p><span style=\"font-weight: 400;\">A simulation can achieve high code coverage while still missing important functional scenarios. Likewise, a carefully designed functional coverage model can show that intended scenarios were exercised while code coverage reveals RTL that the tests never reached.<\/span><\/p><p><span style=\"font-weight: 400;\">Functional coverage is generally defined by the verification team from the specification and test plan, while code coverage is collected from the design implementation by simulation or coverage tools. AMD&#8217;s current Vivado documentation describes functional coverage as a user-defined metric based on features and conditions identified in the test plan.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, understanding both metrics is important because coverage is not just a percentage shown in a report. It is a way to identify what has been exercised, what is still missing, and where the verification plan needs attention.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Code Coverage?<\/span><\/h3><p><b>Code coverage<\/b><span style=\"font-weight: 400;\"> measures which parts or constructs of the RTL were exercised during simulation.<\/span><\/p><p><span style=\"font-weight: 400;\">Depending on the simulator and coverage configuration, code coverage can include metrics such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Statement or line coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Branch coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Condition or expression coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Toggle coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM state coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM transition coverage<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The exact metrics and terminology vary by tool.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0data_out = data_in;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0data_out = &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A test that exercises <\/span><span style=\"font-weight: 400;\">enable = 1<\/span><span style=\"font-weight: 400;\"> may execute the first branch.<\/span><\/p><p><span style=\"font-weight: 400;\">If the testbench never applies <\/span><span style=\"font-weight: 400;\">enable = 0<\/span><span style=\"font-weight: 400;\">, the other branch may remain uncovered.<\/span><\/p><p><span style=\"font-weight: 400;\">Code coverage can therefore help identify RTL paths that have not been exercised.<\/span><\/p><h5><span style=\"font-weight: 400;\">What question does code coverage answer?<\/span><\/h5><p><span style=\"font-weight: 400;\">Primarily:<\/span><\/p><p><b>&#8220;Did simulation execute this part of the implementation?&#8221;<\/b><\/p><p><span style=\"font-weight: 400;\">That is useful because unexecuted RTL deserves investigation.<\/span><\/p><p><span style=\"font-weight: 400;\">However, execution alone does not prove that the behavior was correct.<\/span><\/p><p><span style=\"font-weight: 400;\">A line can execute and still produce an incorrect result.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">What Is Functional Coverage?<\/span><\/h3><p><span style=\"font-weight: 400;\">Functional coverage is a user-defined measurement of whether the scenarios and behaviors considered important in the verification plan have actually occurred.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of starting from the RTL source code, functional coverage starts from the design specification and verification intent.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, suppose an RTL block contains an ALU supporting:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ADD<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SUB<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AND<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">OR<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A functional coverage model could define coverage for each operation.<\/span><\/p><p><span style=\"font-weight: 400;\">It could also define important operand conditions such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Zero<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Maximum value<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimum value<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Positive values<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Negative values<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Equal operands<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Different operands<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The verification team might then create cross coverage to determine whether important combinations occurred.<\/span><\/p><p><span style=\"font-weight: 400;\">SystemVerilog provides constructs such as <\/span><span style=\"font-weight: 400;\">covergroup<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">coverpoint<\/span><span style=\"font-weight: 400;\">, bins and crosses for creating functional coverage models.<\/span><\/p><h5><span style=\"font-weight: 400;\">What question does functional coverage answer?<\/span><\/h5><p><span style=\"font-weight: 400;\">Primarily:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Did we exercise the scenarios and behaviors we intended to verify?&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">This makes functional coverage closely connected to the verification plan.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Functional Coverage vs Code Coverage: The Main Difference<\/span><\/h3><p><span style=\"font-weight: 400;\">The easiest way to remember the distinction is:<\/span><\/p><table><tbody><tr><td><p><b>Aspect<\/b><\/p><\/td><td><p><b>Code Coverage<\/b><\/p><\/td><td><p><b>Functional Coverage<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Main focus<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">RTL implementation<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Design functionality<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Based on<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Source\/compiled RTL<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Specification and verification plan<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Usually created by<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Coverage tool<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Verification engineer<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Measures<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Executed code constructs<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Defined scenarios\/features<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Typical metrics<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Lines, branches, expressions, toggles, FSM<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Values, ranges, transitions, combinations, scenarios<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Requires a coverage model?<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Tool-generated\/instrumented<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Can identify unexecuted RTL?<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Not directly<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Can track a specific requirement?<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Not reliably<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Proves correctness?<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">No<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">No<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Useful for finding test gaps?<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Yes<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">The two metrics are therefore complementary rather than interchangeable.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">A Simple Example: ALU Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider an ALU with four operations:<\/span><\/p><p><span style=\"font-weight: 400;\">ADD<\/span><\/p><p><span style=\"font-weight: 400;\">SUB<\/span><\/p><p><span style=\"font-weight: 400;\">AND<\/span><\/p><p><span style=\"font-weight: 400;\">OR<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Suppose the testbench executes:<\/span><\/p><p><span style=\"font-weight: 400;\">ADD<\/span><\/p><p><span style=\"font-weight: 400;\">ADD<\/span><\/p><p><span style=\"font-weight: 400;\">ADD<\/span><\/p><p><span style=\"font-weight: 400;\">SUB<\/span><\/p><p><span style=\"font-weight: 400;\">SUB<\/span><\/p><p><span style=\"font-weight: 400;\">AND<\/span><\/p><p><span style=\"font-weight: 400;\">OR<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The RTL associated with all four operations may have been executed.<\/span><\/p><p><span style=\"font-weight: 400;\">Code coverage could therefore look very good.<\/span><\/p><p><span style=\"font-weight: 400;\">But what if the verification plan requires testing:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ADD with zero<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ADD with maximum values<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SUB resulting in zero<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">SUB with underflow conditions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AND with all-zero operands<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">AND with all-one operands<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">OR with mixed operands<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">If these scenarios were not deliberately tracked, high code coverage would not tell you that they were missing.<\/span><\/p><p><span style=\"font-weight: 400;\">Functional coverage can.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified coverage model could define:<\/span><\/p><p><span style=\"font-weight: 400;\">covergroup alu_cg;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0cp_opcode: coverpoint opcode;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0cp_operand_type: coverpoint operand_type;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0opcode_x_operand:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0cross cp_opcode, cp_operand_type;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endgroup<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact model should come from the specification and verification plan, not simply from whatever signals happen to be available.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Why 100% Code Coverage Does Not Mean Complete Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">This is one of the most important concepts for a VLSI verification engineer.<\/span><\/p><p><span style=\"font-weight: 400;\">Suppose your simulation reaches every executable RTL statement.<\/span><\/p><p><span style=\"font-weight: 400;\">You might report:<\/span><\/p><p><b>Code coverage = 100%<\/b><\/p><p><span style=\"font-weight: 400;\">That sounds complete, but it does not answer several important questions:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Did every required feature occur?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Did all important input combinations occur?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Were boundary conditions tested?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Were error conditions exercised?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Were protocol corner cases tested?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Did the design produce the expected result?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Were important sequences tested in the correct order?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Code coverage tells you that the implementation was exercised.<\/span><\/p><p><span style=\"font-weight: 400;\">It does <\/span><b>not<\/b><span style=\"font-weight: 400;\"> establish that the specification was completely tested or that every observed result was correct.<\/span><\/p><p><span style=\"font-weight: 400;\">Verification resources similarly emphasize that 100% code coverage does not imply complete functional verification.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Why 100% Functional Coverage Does Not Mean the Design Is Bug-Free<\/span><\/h3><p><span style=\"font-weight: 400;\">Functional coverage has its own limitation.<\/span><\/p><p><span style=\"font-weight: 400;\">Imagine that the verification team defines only these bins:<\/span><\/p><p><span style=\"font-weight: 400;\">ADD<\/span><\/p><p><span style=\"font-weight: 400;\">SUB<\/span><\/p><p><span style=\"font-weight: 400;\">AND<\/span><\/p><p><span style=\"font-weight: 400;\">OR<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">All four bins are hit.<\/span><\/p><p><span style=\"font-weight: 400;\">Functional coverage could report:<\/span><\/p><p><b>100%<\/b><\/p><p><span style=\"font-weight: 400;\">But what if the verification plan forgot an important requirement?<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset behavior was not included.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An illegal opcode scenario was omitted.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A boundary condition was forgotten.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A specific protocol sequence was never modeled.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A required error response was not included.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The coverage model cannot report something it was never asked to measure.<\/span><\/p><p><span style=\"font-weight: 400;\">This is why functional coverage quality depends heavily on the quality of the verification plan and coverage model.<\/span><\/p><p><span style=\"font-weight: 400;\">A high percentage of a poorly defined coverage model is not the same as comprehensive verification.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Code Coverage Metrics VLSI Engineers Should Know<\/span><\/h3><p><span style=\"font-weight: 400;\">Code coverage is not one single metric.<\/span><\/p><h5><span style=\"font-weight: 400;\">1. Statement Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Measures whether executable statements were executed.<\/span><\/p><p><span style=\"font-weight: 400;\">Useful for identifying RTL that was never reached.<\/span><\/p><h5><span style=\"font-weight: 400;\">2. Branch Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Measures whether different decision outcomes were exercised.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">if (valid)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0&#8230;<\/span><\/p><p><span style=\"font-weight: 400;\">else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0&#8230;<\/span><\/p><p><span style=\"font-weight: 400;\">Ideally, verification should exercise both relevant paths.<\/span><\/p><h5><span style=\"font-weight: 400;\">3. Expression or Condition Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Examines conditions within decision expressions.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">if (valid &amp;&amp; ready &amp;&amp; enable)<\/span><\/p><p><span style=\"font-weight: 400;\">A coverage tool can help determine whether relevant condition combinations were exercised, depending on the tool and coverage configuration.<\/span><\/p><h5><span style=\"font-weight: 400;\">4. Toggle Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Measures signal transitions.<\/span><\/p><p><span style=\"font-weight: 400;\">It can help identify signals or bits that never changed during simulation.<\/span><\/p><p><span style=\"font-weight: 400;\">Toggle coverage can be particularly useful for finding signals that may not be adequately exercised, but a toggle does not by itself demonstrate meaningful functional behavior.<\/span><\/p><h5><span style=\"font-weight: 400;\">5. FSM Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">For designs containing finite state machines, coverage may track:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">States reached<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Transitions exercised<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This can reveal state or transition paths that were not reached by the tests.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Functional Coverage Metrics VLSI Engineers Should Know<\/span><\/h3><p><a href=\"https:\/\/inskill.in\/training\/sv-coverage-assertions\/\"><span style=\"font-weight: 400;\">SystemVerilog functional coverage<\/span><\/a><span style=\"font-weight: 400;\"> gives verification engineers more control over what they consider important.<\/span><\/p><h5><span style=\"font-weight: 400;\">Covergroups<\/span><\/h5><p><span style=\"font-weight: 400;\">A <\/span><span style=\"font-weight: 400;\">covergroup<\/span><span style=\"font-weight: 400;\"> defines a functional coverage model.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">covergroup bus_cg;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0&#8230;<\/span><\/p><p><span style=\"font-weight: 400;\">endgroup<\/span><\/p><p><span style=\"font-weight: 400;\">The model can then be instantiated and sampled according to the verification environment.<\/span><\/p><h5><span style=\"font-weight: 400;\">Coverpoints<\/span><\/h5><p><span style=\"font-weight: 400;\">A <\/span><b>coverpoint<\/b><span style=\"font-weight: 400;\"> specifies what value or expression you want to observe.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">cp_opcode: coverpoint opcode;<\/span><\/p><p><span style=\"font-weight: 400;\">The coverpoint can then be divided into bins.<\/span><\/p><h5><span style=\"font-weight: 400;\">Bins<\/span><\/h5><p><span style=\"font-weight: 400;\">Bins group values or conditions that are important to the verification plan.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">cp_size: coverpoint size {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0bins small\u00a0 = {[0:3]};<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0bins medium = {[4:7]};<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0bins large\u00a0 = {[8:15]};<\/span><\/p><p><span style=\"font-weight: 400;\">}<\/span><\/p><p><span style=\"font-weight: 400;\">The exact bins should reflect meaningful design behavior rather than arbitrary ranges.<\/span><\/p><h5><span style=\"font-weight: 400;\">Cross Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Cross coverage measures combinations between coverage points.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">opcode_x_size:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0cross cp_opcode, cp_size;<\/span><\/p><p><span style=\"font-weight: 400;\">This can answer a question such as:<\/span><\/p><p><b>&#8220;Did we test every important operation with every important data-size category?&#8221;<\/b><\/p><p><span style=\"font-weight: 400;\">Cross coverage can become very large, so it should be used selectively.<\/span><\/p><h3><span style=\"font-weight: 400;\">Functional Coverage Is Based on the Verification Plan<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the biggest mistakes beginners make is creating coverage from RTL signals without first understanding the specification.<\/span><\/p><p><span style=\"font-weight: 400;\">A better process is:<\/span><\/p><p><span style=\"font-weight: 400;\">Specification, features, Verification requirements, Coverage plan, Coverpoints \/ bins \/ crosses, Stimulus, Coverage results<\/span><\/p><p><span style=\"font-weight: 400;\">For example, suppose a FIFO specification says:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Empty state must be handled.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Full state must be handled.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Simultaneous read\/write is supported.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Overflow attempts must be handled.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Underflow attempts must be handled.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A functional coverage model could track these scenarios.<\/span><\/p><p><span style=\"font-weight: 400;\">The coverage model therefore reflects what matters from a functional perspective, not simply which RTL signals exist.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Code Coverage and Functional Coverage Can Show Different Results<\/span><\/h3><p><span style=\"font-weight: 400;\">The most useful way to understand the two metrics is to look at combinations.<\/span><\/p><h5><span style=\"font-weight: 400;\">High Code Coverage + Low Functional Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">This can indicate that the tests are exercising much of the RTL but are not covering enough of the scenarios defined in the verification plan.<\/span><\/p><p><span style=\"font-weight: 400;\">Possible reasons include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Missing tests<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Poor stimulus constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Missing corner-case scenarios<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incomplete functional coverage model<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect assumptions in the testbench<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">It should trigger investigation rather than an automatic conclusion.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Low Code Coverage + High Functional Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">This combination can also occur.<\/span><\/p><p><span style=\"font-weight: 400;\">Possible explanations include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The functional model covers a subset of intended scenarios.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Some RTL is not reachable.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">There may be dead or redundant code.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Some implementation paths need additional stimulus.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The coverage model and RTL may not be aligned.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Again, the right response is to investigate the gap.<\/span><\/p><p><span style=\"font-weight: 400;\">Verification Academy discussions specifically caution against treating the two metrics as interchangeable and recommend investigating why the gap exists rather than using the percentages as a simple pass\/fail indicator.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">High Code Coverage + High Functional Coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">This is generally a stronger coverage position, but it still does not prove that verification is complete.<\/span><\/p><p><span style=\"font-weight: 400;\">You still need to consider:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reference models<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Checkers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Negative testing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error injection<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset scenarios<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol compliance<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Performance requirements<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Formal verification where applicable<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Testbench quality<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Specification completeness<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Coverage is evidence about what was exercised.<\/span><\/p><p><span style=\"font-weight: 400;\">It is not a mathematical proof that the design contains no bugs.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">What About Assertions?<\/span><\/h3><p><span style=\"font-weight: 400;\">Assertions and coverage are related, but they serve different purposes.<\/span><\/p><p><span style=\"font-weight: 400;\">An assertion generally checks whether a property is obeyed.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">If VALID is high and READY is low,<\/span><\/p><p><span style=\"font-weight: 400;\">the transfer payload should remain stable.<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A coverage point could instead record:<\/span><\/p><p><span style=\"font-weight: 400;\">Did the VALID-without-READY condition actually occur?<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">So:<\/span><\/p><p><b>Assertion:<\/b><b><br \/><\/b><span style=\"font-weight: 400;\">&#8220;Was the rule obeyed?&#8221;<\/span><\/p><p><b>Coverage:<\/b><b><br \/><\/b><span style=\"font-weight: 400;\">&#8220;Did the situation occur?&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">This distinction is important when building a verification environment.<\/span><\/p><p><a href=\"https:\/\/inskill.in\/training\/vlsi\/assertion-based-verification-abv-explained\/\"><span style=\"font-weight: 400;\">Assertion-based verification<\/span><\/a><span style=\"font-weight: 400;\"> checks properties from coverage constructs, which record that scenarios or conditions occurred.<\/span><\/p><h3><span style=\"font-weight: 400;\">How Code Coverage and Functional Coverage Work Together<\/span><\/h3><p><span style=\"font-weight: 400;\">A practical verification flow might look like this:<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Define the specification<\/span><\/h5><p><span style=\"font-weight: 400;\">Understand what the DUT is supposed to do.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 2: Create the verification plan<\/span><\/h5><p><span style=\"font-weight: 400;\">Identify:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Features<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Modes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Input conditions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Corner cases<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Error conditions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Important sequences<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 3: Build functional coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Translate those requirements into:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Covergroups<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Coverpoints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Bins<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Crosses<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Transition coverage where useful<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 4: Run tests<\/span><\/h5><p><span style=\"font-weight: 400;\">Use directed, constrained-random, regression and other appropriate tests.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 5: Collect code coverage<\/span><\/h5><p><span style=\"font-weight: 400;\">Analyze:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Statements<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Branches<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Expressions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Toggles<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM states\/transitions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">according to the project&#8217;s coverage methodology.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 6: Compare the gaps<\/span><\/h5><p><span style=\"font-weight: 400;\">Ask:<\/span><\/p><p><b>What functionality is missing?<\/b><\/p><p><span style=\"font-weight: 400;\">and:<\/span><\/p><p><b>What RTL remains unexecuted?<\/b><\/p><h5><span style=\"font-weight: 400;\">Step 7: Investigate<\/span><\/h5><p><span style=\"font-weight: 400;\">Do not immediately modify the coverage model just to increase the percentage.<\/span><\/p><p><span style=\"font-weight: 400;\">Determine why the bin or RTL path was missed.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 8: Close legitimate coverage holes<\/span><\/h5><p><span style=\"font-weight: 400;\">Possible actions include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Add stimulus<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Modify constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Add a test<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Improve the coverage model<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Fix unreachable RTL<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Remove genuinely dead code<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Document justified exclusions<\/span><\/li><\/ul><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Coverage Metrics VLSI Engineers Should Remember<\/span><\/h3><table><tbody><tr><td><p><b>Metric<\/b><\/p><\/td><td><p><b>Main question<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Statement coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which executable statements ran?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Branch coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which decision paths ran?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Expression\/condition coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which logical conditions were exercised?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Toggle coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which signal transitions occurred?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">FSM coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which states\/transitions were reached?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Functional coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which specified scenarios\/features occurred?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Cross coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which important combinations occurred?<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Transition coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Which specified value\/state transitions occurred?<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">The availability and exact interpretation of these metrics depend on the simulator and verification methodology.<\/span><\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">Functional coverage and code coverage answer different questions, and a strong VLSI verification strategy uses both.<\/span><\/p><p><span style=\"font-weight: 400;\">Code coverage looks at the implementation:<\/span><\/p><p><span style=\"font-weight: 400;\">Did the simulation execute the RTL?<\/span><\/p><p><span style=\"font-weight: 400;\">Functional coverage looks at the verification intent:<\/span><\/p><p><span style=\"font-weight: 400;\">Did we exercise the important functionality and scenarios identified in the verification plan?<\/span><\/p><p><span style=\"font-weight: 400;\">Neither metric proves correctness by itself.<\/span><\/p><p><span style=\"font-weight: 400;\">A design can execute 100% of its RTL and still miss an important functional scenario. Conversely, a functional coverage model can report 100% while overlooking a requirement that was never included in the model.<\/span><\/p><p><span style=\"font-weight: 400;\">The most useful coverage process is therefore:<\/span><\/p><p><span style=\"font-weight: 400;\">Specification \u2192 Verification Plan \u2192 Functional Coverage \u2192 Stimulus \u2192 Code Coverage \u2192 Gap Analysis \u2192 Coverage Closure<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, the real skill is not achieving an impressive coverage percentage. It is being able to explain what the percentage represents, identify what is missing, understand why it is missing, and decide what action is justified by the verification evidence.<\/span><\/p><p><span style=\"font-weight: 400;\">That is the difference between simply collecting coverage and actually using coverage to improve verification.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>When engineers start learning RTL verification, two coverage terms appear repeatedly: code coverage and functional coverage. Both help a verification team understand how thoroughly a design has been exercised, but they answer different questions. Code coverage asks: Which parts of the RTL were executed? Functional coverage asks: Which features, scenarios, values, combinations, and behaviors defined [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10222","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Functional Coverage vs Code Coverage: VLSI Engineers Must Know<\/title>\n<meta name=\"description\" content=\"Understand functional coverage vs code coverage in VLSI verification, including examples, coverage metrics, SystemVerilog bins, coverage gaps, and practical usage.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" 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