{"id":10234,"date":"2026-09-30T13:02:35","date_gmt":"2026-09-30T13:02:35","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10234"},"modified":"2026-09-29T13:05:29","modified_gmt":"2026-09-29T13:05:29","slug":"how-to-write-systemverilog-assertions-rtl-verification","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/how-to-write-systemverilog-assertions-rtl-verification\/","title":{"rendered":"How to Write Effective SystemVerilog Assertions for RTL Verification"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10234\" class=\"elementor elementor-10234\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-4dafe27 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"4dafe27\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-76d07e4\" data-id=\"76d07e4\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-7ae23ba elementor-widget elementor-widget-text-editor\" data-id=\"7ae23ba\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">A simulation can execute thousands or millions of test scenarios without automatically telling you whether every important RTL behavior was correct.<\/span><\/p><p><span style=\"font-weight: 400;\">This is where <\/span><a href=\"https:\/\/inskill.in\/training\/sv-coverage-assertions\/\"><b>SystemVerilog Assertions (SVA)<\/b><\/a><span style=\"font-weight: 400;\"> become useful.<\/span><\/p><p><span style=\"font-weight: 400;\">Instead of checking every expected behavior manually in a testbench, an assertion lets you express a rule that the design is expected to obey.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Whenever a request is accepted, an acknowledgement must occur within a specified number of clock cycles.<\/span><\/p><p><span style=\"font-weight: 400;\">That requirement can be expressed directly as a temporal property.<\/span><\/p><p><span style=\"font-weight: 400;\">SystemVerilog provides assertions for both immediate and concurrent checking, with concurrent assertions particularly useful for describing relationships between signals over time.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, learning SVA is therefore not just about memorizing operators such as <\/span><span style=\"font-weight: 400;\">|-&gt;<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">|=&gt;<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">##<\/span><span style=\"font-weight: 400;\">, and <\/span><span style=\"font-weight: 400;\">$past()<\/span><span style=\"font-weight: 400;\">. The important skill is learning how to convert a design requirement into a property that checks the right behavior at the right time.<\/span><\/p><p><span style=\"font-weight: 400;\">This guide explains that process with practical RTL examples.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Are SystemVerilog Assertions?<\/span><\/h3><p><span style=\"font-weight: 400;\">A SystemVerilog Assertion is a statement used to specify and check expected behavior in a design or verification environment.<\/span><\/p><p><span style=\"font-weight: 400;\">At a high level:<\/span><\/p><p><span style=\"font-weight: 400;\">Design requirement \u2192 Property \u2192 Assertion \u2192 Pass\/Failure information<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |-&gt; ##1 ack<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This expresses a temporal relationship between <\/span><span style=\"font-weight: 400;\">req<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">ack<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">The exact meaning depends on the implication and timing operators used, which is why understanding SVA semantics is more important than simply copying assertion templates.<\/span><\/p><p><span style=\"font-weight: 400;\">Assertions can be used in simulation and can also be used with <\/span><a href=\"https:\/\/inskill.in\/training\/formal-property-verification\/\"><span style=\"font-weight: 400;\">formal verification tools<\/span><\/a><span style=\"font-weight: 400;\">. <\/span><a href=\"http:\/\/www.accellera.org\" target=\"_blank\" rel=\"noopener\"><span style=\"font-weight: 400;\">Accellera&#8217;s<\/span><\/a><span style=\"font-weight: 400;\"> SVA material specifically describes assertions as useful for protocol checking and functional validation, and notes that they can help localize errors during debug.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Why Use Assertions in RTL Verification?<\/span><\/h3><p><span style=\"font-weight: 400;\">Traditional testbench checking often looks like this:<\/span><\/p><p><span style=\"font-weight: 400;\">Drive stimulus, wait, check output, Report failure.<\/span><\/p><p><span style=\"font-weight: 400;\">Assertions provide another layer of checking:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL activity, Assertion observes behavior, Property evaluated, Pass\/failure reported<\/span><\/p><p><span style=\"font-weight: 400;\">This is particularly useful for properties that should hold continuously throughout a simulation.<\/span><\/p><p><span style=\"font-weight: 400;\">Examples include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A request must eventually receive an acknowledgement.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A FIFO must not report empty and full simultaneously.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data must remain stable while a transfer is stalled.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A state transition must occur only under a specific condition.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A counter must not exceed its defined maximum.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A response must occur within a specified time window.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A protocol signal must not be asserted under an illegal condition.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Assertions can therefore turn design requirements into executable checks.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Immediate vs Concurrent Assertions<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the first distinctions to understand is between immediate assertions and concurrent assertions.<\/span><\/p><h5><span style=\"font-weight: 400;\">Immediate Assertions<\/span><\/h5><p><span style=\"font-weight: 400;\">Immediate assertions are procedural.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0assert (addr &lt; MAX_ADDR)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0else $error(&#8220;Address out of range&#8221;);<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p><span style=\"font-weight: 400;\">The condition is evaluated when the procedural statement executes.<\/span><\/p><p><span style=\"font-weight: 400;\">Immediate assertions are useful for checking conditions at a particular point in procedural execution.<\/span><\/p><h5><span style=\"font-weight: 400;\">Concurrent Assertions<\/span><\/h5><p><span style=\"font-weight: 400;\">Concurrent assertions are designed to describe behavior across clock cycles.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_req_ack;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |-&gt; ##1 ack;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p><span style=\"font-weight: 400;\">assert property (p_req_ack);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is useful when the requirement involves a temporal relationship:<\/span><\/p><p><b>If this happens, something else must happen later.<\/b><\/p><p><span style=\"font-weight: 400;\">Concurrent assertions are particularly useful for:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol checking<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><a href=\"https:\/\/inskill.in\/training\/vlsi\/ready-valid-handshake-protocol-rtl\/\"><span style=\"font-weight: 400;\">Handshake verification<\/span><\/a><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Pipeline timing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Request\/response relationships<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFO conditions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset behavior<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interface protocols<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For most RTL verification work involving cycle-by-cycle behavior, concurrent SVA is an important skill.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Start With the Requirement, Not the Assertion Syntax<\/span><\/h3><p><span style=\"font-weight: 400;\">One of the most common mistakes beginners make is starting with SVA syntax.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, they learn:<\/span><\/p><p><span style=\"font-weight: 400;\">|-&gt;\u00a0<\/span><\/p><p><span style=\"font-weight: 400;\">|=&gt;<\/span><\/p><p><span style=\"font-weight: 400;\">##1<\/span><\/p><p><span style=\"font-weight: 400;\">$past()<\/span><\/p><p><span style=\"font-weight: 400;\">$stable()<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and then try to find places to use them.<\/span><\/p><p><span style=\"font-weight: 400;\">A better process is:<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Write the requirement in plain English<\/span><\/h5><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">If <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is high while <\/span><span style=\"font-weight: 400;\">ready<\/span><span style=\"font-weight: 400;\"> is low, the data must remain unchanged until the transfer occurs.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 2: Identify the sampling clock<\/span><\/h5><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">posedge clk<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 3: Identify the trigger<\/span><\/h5><p><span style=\"font-weight: 400;\">valid &amp;&amp; !ready<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 4: Identify the expected behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">data remains stable<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 5: Convert the requirement into SVA<\/span><\/h5><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_data_stable;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready |=&gt; $stable(data);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This approach produces much more meaningful assertions than starting from syntax.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Understanding the Basic SVA Structure<\/span><\/h3><p><span style=\"font-weight: 400;\">A typical concurrent assertion can be written as:<\/span><\/p><p><span style=\"font-weight: 400;\">property property_name;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0antecedent |-&gt; consequent;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (property_name);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There are three important pieces:<\/span><\/p><h5><span style=\"font-weight: 400;\">Clocking event<\/span><\/h5><p><span style=\"font-weight: 400;\">@(posedge clk)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Defines when the property is sampled.<\/span><\/p><h5><span style=\"font-weight: 400;\">Antecedent<\/span><\/h5><p><span style=\"font-weight: 400;\">The condition that starts the property.<\/span><\/p><p><span style=\"font-weight: 400;\">req<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Consequent<\/span><\/h5><p><span style=\"font-weight: 400;\">The behavior expected after the antecedent occurs.<\/span><\/p><p><span style=\"font-weight: 400;\">ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">So:<\/span><\/p><p><span style=\"font-weight: 400;\">req |-&gt; ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">can be read conceptually as:<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">req<\/span><span style=\"font-weight: 400;\"> occurs, the specified consequent must satisfy the property according to the implication timing.<\/span><\/p><p><span style=\"font-weight: 400;\">The exact timing depends on whether you use overlapped or non-overlapped implication.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">|-&gt; vs |=&gt; in SystemVerilog Assertions<\/span><\/h3><p><span style=\"font-weight: 400;\">This is one of the most important SVA concepts.<\/span><\/p><h5><span style=\"font-weight: 400;\">Overlapped Implication: <\/span><span style=\"font-weight: 400;\">|-&gt;<\/span><\/h5><p><span style=\"font-weight: 400;\">The consequent starts in the same clocking cycle as the antecedent.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">req |-&gt; ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">conceptually means:<\/span><\/p><p><span style=\"font-weight: 400;\">If the antecedent occurs, the consequent is evaluated starting at that same sampled cycle.<\/span><\/p><h5><span style=\"font-weight: 400;\">Non-Overlapped Implication: <\/span><span style=\"font-weight: 400;\">|=&gt;<\/span><\/h5><p><span style=\"font-weight: 400;\">The consequent starts on the following clock cycle.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">req |=&gt; ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">means the consequent starts one clock later.<\/span><\/p><p><span style=\"font-weight: 400;\">A simple way to remember it is:<\/span><\/p><p><span style=\"font-weight: 400;\">|-&gt; \u00a0 same starting cycle<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">|=&gt; \u00a0 next clock cycle<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">When writing an assertion, do not choose the operator because it &#8220;looks right.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">Choose it based on the timing requirement.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using ## for Cycle Delays<\/span><\/h3><p><span style=\"font-weight: 400;\">The <\/span><span style=\"font-weight: 400;\">##<\/span><span style=\"font-weight: 400;\"> operator is used to describe clock-cycle delays.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">req |-&gt; ##1 ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">means that after the antecedent, <\/span><span style=\"font-weight: 400;\">ack<\/span><span style=\"font-weight: 400;\"> is expected one clock step later according to the property semantics.<\/span><\/p><p><span style=\"font-weight: 400;\">Similarly:<\/span><\/p><p><span style=\"font-weight: 400;\">req |-&gt; ##2 ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">describes a two-cycle delay.<\/span><\/p><p><span style=\"font-weight: 400;\">A range can also be used:<\/span><\/p><p><span style=\"font-weight: 400;\">req |-&gt; ##[1:3] ack<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This describes an acknowledgement occurring within the specified temporal window.<\/span><\/p><p><span style=\"font-weight: 400;\">This is particularly useful for interfaces where latency is allowed to vary within a defined range.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 1: Request Must Receive an Acknowledgement<\/span><\/h5><p><span style=\"font-weight: 400;\">Suppose the specification says:<\/span><\/p><p><span style=\"font-weight: 400;\">Every request must receive an acknowledgement within two to four clock cycles.<\/span><\/p><p><span style=\"font-weight: 400;\">A corresponding property could be:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_req_ack;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |-&gt; ##[2:4] ack;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_req_ack);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The important point is that the assertion directly reflects the requirement.<\/span><\/p><p><span style=\"font-weight: 400;\">Before writing it, confirm:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What exactly constitutes a request?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can multiple requests be outstanding?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can an acknowledgement arrive earlier?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can acknowledgements be reordered?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does reset cancel an outstanding request?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The SVA should reflect the actual protocol, not an assumed simplified version.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 2: Valid\/Ready Handshake<\/span><\/h5><p><span style=\"font-weight: 400;\">Consider a standard ready\/valid interface.<\/span><\/p><p><span style=\"font-weight: 400;\">A transfer occurs when:<\/span><\/p><p><span style=\"font-weight: 400;\">valid &amp;&amp; ready<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Suppose the requirement is:<\/span><\/p><p><span style=\"font-weight: 400;\">When <\/span><span style=\"font-weight: 400;\">valid<\/span><span style=\"font-weight: 400;\"> is asserted and the receiver is not ready, the source must keep the payload stable.<\/span><\/p><p><span style=\"font-weight: 400;\">A useful assertion is:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_valid_data_stable;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready |=&gt; $stable(data);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_valid_data_stable);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is an example of an assertion that checks a <\/span><b>protocol rule<\/b><span style=\"font-weight: 400;\">, not merely an output value.<\/span><\/p><p><span style=\"font-weight: 400;\">It can be particularly useful for AXI-style interfaces and custom streaming interfaces.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 3: FIFO Must Not Read When Empty<\/span><\/h5><p><span style=\"font-weight: 400;\">Suppose a FIFO should never accept a read request when it is empty.<\/span><\/p><p><span style=\"font-weight: 400;\">You could express the requirement as:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_no_read_when_empty;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0empty |-&gt; !rd_en;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_no_read_when_empty);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">However, the exact property depends on how <\/span><span style=\"font-weight: 400;\">rd_en<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">empty<\/span><span style=\"font-weight: 400;\">, and the FIFO interface are defined.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if the FIFO accepts a read only when:<\/span><\/p><p><span style=\"font-weight: 400;\">rd_en &amp;&amp; !empty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">then the property should be aligned with that transaction definition.<\/span><\/p><p><span style=\"font-weight: 400;\">This illustrates an important SVA principle:<\/span><\/p><p><b>The assertion must match the actual interface contract.<\/b><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 4: FIFO Cannot Be Full and Empty Simultaneously<\/span><\/h5><p><span style=\"font-weight: 400;\">For a FIFO where <\/span><span style=\"font-weight: 400;\">full<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">empty<\/span><span style=\"font-weight: 400;\"> are mutually exclusive:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_full_empty_mutex;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0!(full &amp;&amp; empty);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_full_empty_mutex);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is a simple example of an invariant.<\/span><\/p><p><span style=\"font-weight: 400;\">An invariant describes something that should remain true whenever the property is checked.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 5: Counter Should Not Exceed a Limit<\/span><\/h5><p><span style=\"font-weight: 400;\">Suppose:<\/span><\/p><p><span style=\"font-weight: 400;\">logic [7:0] count;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">and the counter must never exceed 100.<\/span><\/p><p><span style=\"font-weight: 400;\">You can write:<\/span><\/p><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0count &lt;= 8&#8217;d100<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is useful for catching unexpected state or arithmetic behavior.<\/span><\/p><p><span style=\"font-weight: 400;\">However, if the counter is allowed to temporarily exceed the value before being corrected, the assertion would be incorrect.<\/span><\/p><p><span style=\"font-weight: 400;\">Again, the property must reflect the actual specification.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Example 6: Reset Should Clear a Register<\/span><\/h5><p><span style=\"font-weight: 400;\">Suppose the specification says:<\/span><\/p><p><span style=\"font-weight: 400;\">On the first active clock edge after reset is asserted, <\/span><span style=\"font-weight: 400;\">state<\/span><span style=\"font-weight: 400;\"> must be zero.<\/span><\/p><p><span style=\"font-weight: 400;\">A simple property might be:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_reset_state;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0reset |=&gt; state == IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_reset_state);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">But reset behavior requires particular care because different designs use:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Synchronous reset<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Asynchronous reset<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Active-high reset<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Active-low reset<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">The assertion must use the same reset semantics as the RTL.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using disable iff for Reset<\/span><\/h3><p><span style=\"font-weight: 400;\">For many concurrent assertions, reset should be handled explicitly.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_req_ack;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |-&gt; ##[1:3] ack;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_req_ack);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">disable iff<\/span><span style=\"font-weight: 400;\"> can abort an assertion attempt when the specified condition becomes true. This is particularly useful for preventing a property that started before reset from generating an irrelevant failure after reset changes the design state.<\/span><\/p><p><span style=\"font-weight: 400;\">This is different from simply putting the reset condition in the antecedent.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">!rst_n &amp;&amp; req |-&gt; &#8230;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">only affects whether a new attempt begins.<\/span><\/p><p><span style=\"font-weight: 400;\">It does not provide the same behavior for an assertion attempt that is already in progress when reset occurs.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using $past() in SVA<\/span><\/h3><p><span style=\"font-weight: 400;\">$past()<\/span><span style=\"font-weight: 400;\"> allows an assertion to refer to a sampled value from an earlier clock cycle.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0enable |-&gt; data_out == $past(data_in)<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact timing needs to be carefully defined.<\/span><\/p><p><span style=\"font-weight: 400;\">A more useful example is checking that a control condition resulted in a state change on the following cycle:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_enable_update;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0enable |=&gt; data_out == $past(data_in);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">When using <\/span><span style=\"font-weight: 400;\">$past()<\/span><span style=\"font-weight: 400;\">, always draw the timing on paper first.<\/span><\/p><p><span style=\"font-weight: 400;\">Ask:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which cycle is the antecedent sampled?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which cycle is the consequent sampled?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Which cycle does <\/span><span style=\"font-weight: 400;\">$past()<\/span><span style=\"font-weight: 400;\"> refer to?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This avoids many off-by-one errors.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using $stable() to Check Data Stability<\/span><\/h3><p><span style=\"font-weight: 400;\">$stable()<\/span><span style=\"font-weight: 400;\"> is useful when a signal should not change between samples.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_stable_when_stalled;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready |=&gt; $stable(data);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is particularly useful for:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Ready\/valid interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Pipeline interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Bus protocols<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFO interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Control\/data relationships<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Again, make sure the stability requirement actually exists in the protocol or design specification.<\/span><\/p><p><span style=\"font-weight: 400;\">Do not add <\/span><span style=\"font-weight: 400;\">$stable()<\/span><span style=\"font-weight: 400;\"> simply because a signal &#8220;usually shouldn&#8217;t change.&#8221;<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using $rose() and $fell()<\/span><\/h3><p><span style=\"font-weight: 400;\">$rose()<\/span><span style=\"font-weight: 400;\"> detects a sampled rising transition.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0$rose(req) |=&gt; ack<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Similarly, <\/span><span style=\"font-weight: 400;\">$fell()<\/span><span style=\"font-weight: 400;\"> can be used when the falling transition matters.<\/span><\/p><p><span style=\"font-weight: 400;\">These functions can be useful for requirements such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A request rising edge starts an operation.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A state signal must respond after a transition.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">An enable falling edge triggers a defined behavior.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Be careful with sampled transitions: the assertion observes values according to SystemVerilog&#8217;s assertion sampling semantics, not simply an arbitrary simulator event.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Sequences: Making Assertions Easier to Read<\/span><\/h3><p><span style=\"font-weight: 400;\">As assertions become more complex, repeating the same signal patterns makes the code difficult to maintain.<\/span><\/p><p><span style=\"font-weight: 400;\">A sequence allows a temporal pattern to be named and reused.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">sequence req_accepted;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req &amp;&amp; ready;<\/span><\/p><p><span style=\"font-weight: 400;\">endsequence<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">You can then use it in a property:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_response;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req_accepted |-&gt; ##2 response;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Sequences are particularly useful when several assertions depend on the same protocol event.<\/span><\/p><p><span style=\"font-weight: 400;\">Accellera&#8217;s SVA guidance specifically discusses temporal sequence composition and sequence reuse as part of assertion planning and coding practices.<\/span><\/p><h3><span style=\"font-weight: 400;\">How to Write Effective SystemVerilog Assertions Properties<\/span><\/h3><p><span style=\"font-weight: 400;\">A practical process is:<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Start With the Specification<\/span><\/h5><p><span style=\"font-weight: 400;\">Write the requirement in plain English.<\/span><\/p><p><span style=\"font-weight: 400;\">Example:<\/span><\/p><p><span style=\"font-weight: 400;\">When a transaction is accepted, the response must arrive within three cycles.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 2: Identify the Trigger<\/span><\/h5><p><span style=\"font-weight: 400;\">What starts the requirement?<\/span><\/p><p><span style=\"font-weight: 400;\">valid &amp;&amp; ready<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 3: Identify the Expected Result<\/span><\/h5><p><span style=\"font-weight: 400;\">response<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 4: Define Timing<\/span><\/h5><p><span style=\"font-weight: 400;\">1 to 3 cycles<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 5: Define Exceptions<\/span><\/h5><p><span style=\"font-weight: 400;\">Does reset cancel the requirement?<\/span><\/p><p><span style=\"font-weight: 400;\">disable iff (!rst_n)<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 6: Write the Property<\/span><\/h5><p><span style=\"font-weight: 400;\">property p_transaction_response;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0(valid &amp;&amp; ready) |-&gt; ##[1:3] response;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 7: Add the Assertion<\/span><\/h5><p><span style=\"font-weight: 400;\">assert property (p_transaction_response)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else $error(&#8220;Transaction response timing violation&#8221;);<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 8: Add Coverage if Needed<\/span><\/h5><p><span style=\"font-weight: 400;\">cover property (p_transaction_response);<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Step 9: Test the Assertion Itself<\/span><\/h5><p><span style=\"font-weight: 400;\">Intentionally create a failing scenario.<\/span><\/p><p><span style=\"font-weight: 400;\">If the assertion never fails when the requirement is deliberately violated, the property may be incorrect.<\/span><\/p><p><span style=\"font-weight: 400;\">This is an extremely important verification practice.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Example: Writing Assertions for an AXI-Style Handshake<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider a simple interface:<\/span><\/p><p><span style=\"font-weight: 400;\">valid<\/span><\/p><p><span style=\"font-weight: 400;\">ready<\/span><\/p><p><span style=\"font-weight: 400;\">data<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The first property might check that the payload remains stable when the sender is waiting.<\/span><\/p><p><span style=\"font-weight: 400;\">property p_data_stable;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready |=&gt; $stable(data);<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (p_data_stable);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A second property can cover the stall condition:<\/span><\/p><p><span style=\"font-weight: 400;\">cover property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0valid &amp;&amp; !ready<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This gives you both:<\/span><\/p><p><b>Check:<\/b><span style=\"font-weight: 400;\"> Data remains stable.<\/span><\/p><p><b>Coverage:<\/b><span style=\"font-weight: 400;\"> The stalled condition actually occurred.<\/span><\/p><p><span style=\"font-weight: 400;\">That combination is much more useful than the assertion alone.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Example: FIFO Assertions<\/span><\/h3><p><span style=\"font-weight: 400;\">For a FIFO, you could define properties such as:<\/span><\/p><h5><span style=\"font-weight: 400;\">No read while empty<\/span><\/h5><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0empty |-&gt; !rd_en<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">No write while full<\/span><\/h5><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0disable iff (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0full |-&gt; !wr_en<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Full and empty cannot both be active<\/span><\/h5><p><span style=\"font-weight: 400;\">assert property (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0!(full &amp;&amp; empty)<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The exact properties should be adapted to the FIFO&#8217;s interface contract. For example, some FIFO architectures may accept a write and update the status flag in the same cycle, so the property must account for the actual sampling and update semantics.<\/span><\/p><p><span style=\"font-weight: 400;\">This is an important lesson:<\/span><\/p><p><span style=\"font-weight: 400;\">Do not copy an assertion simply because it looks logically reasonable.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using Assertions During Simulation<\/span><\/h3><p><span style=\"font-weight: 400;\">In simulation, assertions can provide immediate feedback when a property is violated.<\/span><\/p><p><span style=\"font-weight: 400;\">A typical flow is:<\/span><\/p><p><span style=\"font-weight: 400;\">RTL<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Simulation<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">SVA checks<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Assertion failure<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Waveform analysis<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">Root-cause debug<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is useful for catching:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Protocol violations<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unexpected state transitions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect latency<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Data stability issues<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset problems<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Illegal combinations<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Assertions can therefore reduce the amount of manual waveform inspection required during debugging.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Using SVA With Formal Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">Assertions can also be used as properties for formal verification.<\/span><\/p><p><span style=\"font-weight: 400;\">In a formal environment, the tool can explore many possible input and state combinations subject to the environment assumptions.<\/span><\/p><p><span style=\"font-weight: 400;\">This can be particularly useful for properties such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A FIFO never overflows<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A protocol rule is always maintained<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A state machine never reaches an illegal state<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A request eventually produces a response under stated assumptions<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Accellera&#8217;s SVA tutorial explicitly covers the use of SVA in formal verification as well as simulation-oriented assertion development.<\/span><\/p><p><span style=\"font-weight: 400;\">The important difference is that formal and simulation exercise properties differently:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Simulation checks behavior for the scenarios actually generated.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Formal tools can mathematically explore a defined state\/input space subject to assumptions.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Neither approach eliminates the need for a well-defined specification.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Assertions Should Be Reusable<\/span><\/h3><p><span style=\"font-weight: 400;\">For larger projects, create reusable properties and sequences instead of writing every assertion from scratch.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">sequence req_accepted;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req &amp;&amp; ready;<\/span><\/p><p><span style=\"font-weight: 400;\">endsequence<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Then:<\/span><\/p><p><span style=\"font-weight: 400;\">property p_response;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req_accepted |-&gt; ##[1:3] response;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The same sequence can potentially be reused by several properties.<\/span><\/p><p><span style=\"font-weight: 400;\">Accellera&#8217;s guidance on SVA planning specifically includes sequence reuse and parameterization as useful aspects of assertion methodology.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">How to Debug an Assertion Failure<\/span><\/h3><p><span style=\"font-weight: 400;\">An assertion failure is not necessarily the same thing as an RTL bug.<\/span><\/p><p><span style=\"font-weight: 400;\">Start with the property.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 1: Read the failure message<\/span><\/h5><p><span style=\"font-weight: 400;\">Identify:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Property name<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Simulation time<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock cycle<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Relevant signals<\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Step 2: Check the antecedent<\/span><\/h5><p><span style=\"font-weight: 400;\">Did the condition that starts the property actually occur?<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 3: Check the timing<\/span><\/h5><p><span style=\"font-weight: 400;\">Was the consequent checked in the intended cycle?<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 4: Inspect reset<\/span><\/h5><p><span style=\"font-weight: 400;\">Did reset interrupt the property?<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 5: Inspect the waveform<\/span><\/h5><p><span style=\"font-weight: 400;\">Look backward from the failure.<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 6: Check the specification<\/span><\/h5><p><span style=\"font-weight: 400;\">Is the assertion itself correct?<\/span><\/p><h5><span style=\"font-weight: 400;\">Step 7: Classify the failure<\/span><\/h5><p><span style=\"font-weight: 400;\">It could be:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RTL bug<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Testbench problem<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect assertion<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect assumption<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reset interaction<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unsupported scenario<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Specification ambiguity<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This is why good assertion writing and good assertion debugging are closely connected.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Assertions vs Scoreboards vs Functional Coverage<\/span><\/h3><p><span style=\"font-weight: 400;\">These verification techniques serve different purposes.<\/span><\/p><table><tbody><tr><td><p><b>Technique<\/b><\/p><\/td><td><p><b>Main purpose<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Assertion<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Check a specific property<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Scoreboard<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Compare actual and expected transactions\/data<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Functional coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Measure whether planned scenarios occurred<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Code coverage<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Measure which RTL constructs were exercised<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Reference model<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Generate expected behavior<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">Formal verification<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Prove properties over a defined state\/input space<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">A robust verification environment can use several of these together.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">Stimulus<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2193<\/span><\/p><p><span style=\"font-weight: 400;\">DUT<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u251c\u2500\u2500\u2192 Assertions<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u251c\u2500\u2500\u2192 Scoreboard<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u251c\u2500\u2500\u2192 Functional Coverage<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u2514\u2500\u2500\u2192 Code Coverage<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">No single metric or checking mechanism answers every verification question.<\/span><\/p><h3><span style=\"font-weight: 400;\">Common SVA Operators to Know<\/span><\/h3><table><tbody><tr><td><p><b>Operator \/ construct<\/b><\/p><\/td><td><p><b>Typical purpose<\/b><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">`<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">-&gt;`<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">`<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">=&gt;`<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">##<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Cycle delay<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">[*]<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Consecutive repetition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">[-&gt;]<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Goto repetition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">[=]<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Non-consecutive repetition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">$past()<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Access a previous sampled value<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">$stable()<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Check that a value has not changed<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">$rose()<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Detect sampled rising transition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">$fell()<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Detect sampled falling transition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">$changed()<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Detect sampled value change<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">disable iff<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Disable\/abort property evaluation under a condition<\/span><\/p><\/td><\/tr><tr><td><p><span style=\"font-weight: 400;\">cover property<\/span><\/p><\/td><td><p><span style=\"font-weight: 400;\">Check whether a property scenario occurs<\/span><\/p><\/td><\/tr><\/tbody><\/table><p><span style=\"font-weight: 400;\">The exact semantics of temporal operators matter, so engineers should consult the SystemVerilog language reference when a property has subtle timing behavior rather than relying solely on shorthand descriptions.<\/span><\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">Effective SystemVerilog Assertions are not about writing the most complicated temporal expressions.<\/span><\/p><p><span style=\"font-weight: 400;\">They are about converting clear RTL requirements into precise, executable properties.<\/span><\/p><p><span style=\"font-weight: 400;\">A good process is:<\/span><\/p><p><span style=\"font-weight: 400;\">Specification, Plain-language requirement, Identify clock and trigger, Define timing relationship, Write the SVA property, Handle reset and legal exceptions, Assert the property, Cover the scenario where appropriate, Debug failures against the specification<\/span><\/p><p><span style=\"font-weight: 400;\">The most important SVA concepts to master are:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Properties<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Sequences<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">|-&gt;<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">|=&gt;<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">##<\/span><span style=\"font-weight: 400;\"> delays<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">$past()<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">$stable()<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">$rose()<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">$fell()<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">disable iff<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">cover property<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reusable assertion sequences<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Most importantly, do not measure the quality of an assertion by how complex its syntax looks.<\/span><\/p><p><span style=\"font-weight: 400;\">A short assertion that precisely captures a critical protocol rule can be more valuable than a complicated property that is difficult to understand or maintain.<\/span><\/p><p><span style=\"font-weight: 400;\">For VLSI engineers, the real skill is being able to look at an RTL requirement such as:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Data must remain stable until the receiver accepts the transfer.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">and turn it into a property that can continuously check that requirement during simulation or formal analysis.<\/span><\/p><p><span style=\"font-weight: 400;\">That is where SystemVerilog Assertions become a practical RTL verification tool rather than simply another language feature.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>A simulation can execute thousands or millions of test scenarios without automatically telling you whether every important RTL behavior was correct. This is where SystemVerilog Assertions (SVA) become useful. Instead of checking every expected behavior manually in a testbench, an assertion lets you express a rule that the design is expected to obey. For example: [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10234","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>How to Write Effective SystemVerilog Assertions for RTL Verification<\/title>\n<meta name=\"description\" content=\"Learn how to write effective SystemVerilog Assertions for RTL verification with practical SVA examples covering properties, sequences, timing, reset, handshakes, and common mistakes.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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