{"id":10270,"date":"2026-10-06T10:54:22","date_gmt":"2026-10-06T10:54:22","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10270"},"modified":"2026-10-06T11:19:52","modified_gmt":"2026-10-06T11:19:52","slug":"top-systemverilog-coding-questions-vlsi-interviews","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/","title":{"rendered":"Top SystemVerilog Coding Questions Asked in VLSI Interviews"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10270\" class=\"elementor elementor-10270\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-e979b5b elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"e979b5b\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-4ea117b\" data-id=\"4ea117b\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-05d8f6c elementor-widget elementor-widget-text-editor\" data-id=\"05d8f6c\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">SystemVerilog interviews are often more practical than candidates expect. Knowing the syntax of <\/span><span style=\"font-weight: 400;\">logic<\/span><span style=\"font-weight: 400;\">, <\/span><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\">, classes, constraints, or assertions is useful, but interviewers frequently ask candidates to <\/span><b>write code, modify existing code, identify a bug, or explain what the code actually does<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">For RTL design and functional verification roles, coding questions can range from simple sequential logic to SystemVerilog-specific features such as interfaces, queues, randomization, constraints, assertions, functional coverage, and object-oriented programming.<\/span><\/p><p><span style=\"font-weight: 400;\">The important point is that an interviewer is usually evaluating more than whether the code compiles. They want to know whether you understand <\/span><b>hardware behavior, simulation semantics, synthesizability, corner cases, and verification intent<\/b><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">This article covers practical <\/span><a href=\"https:\/\/vlsiguru.com\/interview-preparation-courses\/functional-verification-interview-preparation\"><b>SystemVerilog coding<\/b><\/a><span style=\"font-weight: 400;\"> questions commonly relevant to VLSI interviews, with examples and the kinds of follow-up questions you should expect.<\/span><\/p><h3><span style=\"font-weight: 400;\">1. Write SystemVerilog code for a D flip-flop with reset<\/span><\/h3><p><span style=\"font-weight: 400;\">This is one of the simplest questions, but it tests whether you understand sequential logic and SystemVerilog procedural blocks.<\/span><\/p><h5><span style=\"font-weight: 400;\">Example<\/span><\/h5><p><span style=\"font-weight: 400;\">module dff (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic clk,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic rst_n,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic d,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic q<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0q &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endmodule<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interviewer may immediately ask:<\/span><\/p><p><b>Why did you use <\/b><b>always_ff<\/b><b> and <\/b><b>&lt;=<\/b><b>?<\/b><\/p><p><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\"> clearly communicates that the block represents flip-flop-based sequential logic. The nonblocking assignment models the simultaneous update behavior expected from sequential elements.<\/span><\/p><p><span style=\"font-weight: 400;\">They may then change the requirement:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Make the reset asynchronous.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">The sensitivity list would become:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk or negedge rst_n)<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The important skill is not memorizing both versions. You should be able to modify the code when the specification changes.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">2. Write a parameterized counter<\/span><\/h3><p><span style=\"font-weight: 400;\">A common coding exercise is to write a counter that can be configured for different widths.<\/span><\/p><h5><span style=\"font-weight: 400;\">Example<\/span><\/h5><p><span style=\"font-weight: 400;\">module counter #(<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0parameter int WIDTH = 8<\/span><\/p><p><span style=\"font-weight: 400;\">) (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 clk,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 rst_n,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 enable,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic [WIDTH-1:0] count<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0count &lt;= &#8216;0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0else if (enable)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0count &lt;= count + 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endmodule<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interviewer may ask:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What happens when the counter reaches its maximum value?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">How would you create a down counter?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">How would you make it saturate instead of wrap around?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What does <\/span><span style=\"font-weight: 400;\">&#8216;0<\/span><span style=\"font-weight: 400;\"> do?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Why is the counter parameterized?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For an <\/span><span style=\"font-weight: 400;\">N<\/span><span style=\"font-weight: 400;\">-bit unsigned counter, normal binary arithmetic naturally wraps when the maximum representable value is exceeded.<\/span><\/p><p><span style=\"font-weight: 400;\">A good candidate should also recognize that parameterization makes the RTL reusable rather than hard-coding an 8-bit implementation.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">3. Write a 2:1 multiplexer using <\/span><span style=\"font-weight: 400;\">always_comb<\/span><\/h3><p><span style=\"font-weight: 400;\">This tests basic combinational RTL coding.<\/span><\/p><p><span style=\"font-weight: 400;\">module mux2 (<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic a,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic b,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0input\u00a0 logic sel,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0output logic y<\/span><\/p><p><span style=\"font-weight: 400;\">);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = b;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = a;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endmodule<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A follow-up question may be:<\/span><\/p><p><b>&#8220;Why use <\/b><b>always_comb<\/b><b> instead of <\/b><b>always @(*)<\/b><b>?&#8221;<\/b><\/p><p><span style=\"font-weight: 400;\">always_comb<\/span><span style=\"font-weight: 400;\"> is a SystemVerilog construct specifically intended for combinational logic. It makes design intent clearer and provides additional language-level checking compared with traditional Verilog procedural blocks.<\/span><\/p><p><span style=\"font-weight: 400;\">The interviewer may then intentionally remove the <\/span><span style=\"font-weight: 400;\">else<\/span><span style=\"font-weight: 400;\"> statement:<\/span><\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (sel)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0y = b;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">You should identify the problem: when <\/span><span style=\"font-weight: 400;\">sel<\/span><span style=\"font-weight: 400;\"> is false, <\/span><span style=\"font-weight: 400;\">y<\/span><span style=\"font-weight: 400;\"> is not assigned in that procedural execution, potentially causing latch inference.<\/span><\/p><p><span style=\"font-weight: 400;\">This type of modification question is often more valuable than simply asking you to write a mux from scratch.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">4. What is wrong with this sequential code?<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q1 = d;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q2 = q1;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">An interviewer may ask whether this is correct.<\/span><\/p><p><span style=\"font-weight: 400;\">The preferred sequential coding style is:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q1 &lt;= d;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0q2 &lt;= q1;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">With nonblocking assignments, both registers update based on their values before the clock event.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore:<\/span><\/p><p><span style=\"font-weight: 400;\">Before clock:<\/span><\/p><p><span style=\"font-weight: 400;\">q1 = 0<\/span><\/p><p><span style=\"font-weight: 400;\">q2 = 0<\/span><\/p><p><span style=\"font-weight: 400;\">d\u00a0 = 1<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">After clock:<\/span><\/p><p><span style=\"font-weight: 400;\">q1 = 1<\/span><\/p><p><span style=\"font-weight: 400;\">q2 = 0<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">On the next clock, <\/span><span style=\"font-weight: 400;\">q2<\/span><span style=\"font-weight: 400;\"> can receive the previous value of <\/span><span style=\"font-weight: 400;\">q1<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">This is a classic interview question because it tests whether you understand simulation scheduling and sequential hardware behavior, rather than simply knowing assignment syntax.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">5. Write an FSM using SystemVerilog<\/span><\/h3><p><span style=\"font-weight: 400;\">Finite-state-machine coding is another common RTL exercise.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, suppose an FSM has three states:<\/span><\/p><p><span style=\"font-weight: 400;\">IDLE \u2192 ACTIVE \u2192 DONE<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2191\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 |<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u2514\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2518<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A SystemVerilog implementation can separate state storage from next-state logic.<\/span><\/p><p><span style=\"font-weight: 400;\">typedef enum logic [1:0] {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0IDLE,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0ACTIVE,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0DONE<\/span><\/p><p><span style=\"font-weight: 400;\">} state_t;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">state_t state, next_state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk or negedge rst_n) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0if (!rst_n)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0state &lt;= IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0else<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0state &lt;= next_state;<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">always_comb begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0next_state = state;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case (state)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0IDLE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (start)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = ACTIVE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0ACTIVE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if (complete)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = DONE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0DONE: begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default:<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0next_state = IDLE;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interviewer may ask:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Why use <\/span><span style=\"font-weight: 400;\">typedef enum<\/span><span style=\"font-weight: 400;\">?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Why separate state and next-state logic?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What happens if an illegal state occurs?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Why assign <\/span><span style=\"font-weight: 400;\">next_state = state<\/span><span style=\"font-weight: 400;\"> initially?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Could this code infer a latch?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">This question tests coding style, FSM understanding, reset behavior, and completeness of combinational assignments.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">6. Write a SystemVerilog constraint for random values<\/span><\/h3><p><span style=\"font-weight: 400;\">SystemVerilog coding interviews for verification roles often move beyond RTL into constrained randomization.<\/span><\/p><p><span style=\"font-weight: 400;\">Suppose you need to generate an 8-bit address between <\/span><span style=\"font-weight: 400;\">0<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">255<\/span><span style=\"font-weight: 400;\">, but only even addresses are allowed.<\/span><\/p><p><span style=\"font-weight: 400;\">class transaction;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0rand bit [7:0] addr;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0constraint addr_c {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0addr[0] == 1&#8217;b0;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endclass<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The least significant bit of an even number is zero, so this constraint restricts the generated addresses accordingly.<\/span><\/p><p><span style=\"font-weight: 400;\">You could also express a range:<\/span><\/p><p><span style=\"font-weight: 400;\">constraint addr_range {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0addr inside {[8&#8217;h20:8&#8217;h7F]};<\/span><\/p><p><span style=\"font-weight: 400;\">}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">A likely follow-up question is:<\/span><\/p><p><b>What happens if the constraints conflict?<\/b><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">constraint c1 {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0addr inside {[0:10]};<\/span><\/p><p><span style=\"font-weight: 400;\">}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">constraint c2 {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0addr &gt; 20;<\/span><\/p><p><span style=\"font-weight: 400;\">}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">There is no valid value satisfying both constraints, so randomization fails.<\/span><\/p><p><span style=\"font-weight: 400;\">A verification engineer should know how to detect and debug such situations rather than assuming <\/span><span style=\"font-weight: 400;\">randomize()<\/span><span style=\"font-weight: 400;\"> always succeeds.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">7. Write a class with a constructor and method<\/span><\/h3><p><span style=\"font-weight: 400;\">SystemVerilog supports object-oriented programming, which is particularly important in verification environments.<\/span><\/p><h5><span style=\"font-weight: 400;\">Example<\/span><\/h5><p><span style=\"font-weight: 400;\">class packet;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0bit [7:0] addr;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0bit [31:0] data;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0function new(bit [7:0] addr,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0bit [31:0] data);<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0this.addr = addr;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0this.data = data;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endfunction<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0function void display();<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0$display(&#8220;ADDR = %0h DATA = %0h&#8221;, addr, data);<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endfunction<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endclass<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">An interviewer may ask:<\/span><\/p><p><b>Why use <\/b><b>this.addr<\/b><b> instead of simply <\/b><b>addr<\/b><b>?<\/b><\/p><p><span style=\"font-weight: 400;\">this<\/span><span style=\"font-weight: 400;\"> refers to the current object. Here, it distinguishes the class property from the constructor argument having the same name.<\/span><\/p><p><span style=\"font-weight: 400;\">They may then ask you to create an object:<\/span><\/p><p><span style=\"font-weight: 400;\">packet p;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">initial begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0p = new(8&#8217;h20, 32&#8217;h1234_ABCD);<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0p.display();<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is a basic example, but it tests whether you understand object creation, constructors, class properties, and methods.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">8. How would you use a SystemVerilog interface?<\/span><\/h3><p><span style=\"font-weight: 400;\">Interfaces are frequently discussed in verification-oriented SystemVerilog interviews because they group related signals and simplify communication between the DUT and testbench.<\/span><\/p><h5><span style=\"font-weight: 400;\">Example<\/span><\/h5><p><span style=\"font-weight: 400;\">interface bus_if(input logic clk);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0logic\u00a0 \u00a0 \u00a0 \u00a0 valid;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0logic\u00a0 \u00a0 \u00a0 \u00a0 ready;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0logic [31:0] data;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endinterface<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interface can then be connected to a DUT or used by verification components.<\/span><\/p><p><span style=\"font-weight: 400;\">A common follow-up question is:<\/span><\/p><p><b>What problem does an interface solve?<\/b><\/p><p><span style=\"font-weight: 400;\">Instead of passing many related signals individually between components, the interface groups them into a single reusable communication structure.<\/span><\/p><p><span style=\"font-weight: 400;\">SystemVerilog testbench guidance also highlights interfaces as an important way of simplifying signal connectivity in larger verification environments.<\/span><\/p><p><span style=\"font-weight: 400;\">For a verification interview, you should also be prepared for questions about modports and virtual interfaces.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">9. Write a SystemVerilog assertion for a request-acknowledge protocol<\/span><\/h3><p><span style=\"font-weight: 400;\">Assertions are another important coding area.<\/span><\/p><p><span style=\"font-weight: 400;\">Suppose the requirement is:<\/span><\/p><p><span style=\"font-weight: 400;\">Whenever <\/span><span style=\"font-weight: 400;\">req<\/span><span style=\"font-weight: 400;\"> is asserted, <\/span><span style=\"font-weight: 400;\">ack<\/span><span style=\"font-weight: 400;\"> must be asserted in the next cycle.<\/span><\/p><p><span style=\"font-weight: 400;\">A simple concurrent assertion is:<\/span><\/p><p><span style=\"font-weight: 400;\">property req_ack;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |=&gt; ack;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (req_ack);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">If the requirement instead says that the acknowledgement must occur within one to three cycles, you could express a temporal window:<\/span><\/p><p><span style=\"font-weight: 400;\">property req_ack_window;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0@(posedge clk)<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0req |-&gt; ##[1:3] ack;<\/span><\/p><p><span style=\"font-weight: 400;\">endproperty<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">assert property (req_ack_window);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interviewer may ask about the difference between <\/span><span style=\"font-weight: 400;\">|-&gt;<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">|=&gt;<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">You should be able to explain that they differ in when the consequent begins relative to the antecedent.<\/span><\/p><p><a href=\"https:\/\/inskill.in\/training\/vlsi\/how-to-write-systemverilog-assertions-rtl-verification\/\"><span style=\"font-weight: 400;\">SystemVerilog Assertions<\/span><\/a><span style=\"font-weight: 400;\"> are particularly useful for checking temporal behavior such as handshakes, FIFO conditions, pipeline relationships, reset behavior, and protocol rules.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">10. Write a functional coverage model<\/span><\/h3><p><span style=\"font-weight: 400;\">A coding interview for a verification role may ask you to write a small coverage model.<\/span><\/p><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">covergroup bus_cg @(posedge clk);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0cp_valid: coverpoint valid;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0cp_ready: coverpoint ready;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0cp_data: coverpoint data {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0bins low\u00a0 = {[0:63]};<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0bins mid\u00a0 = {[64:191]};<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0bins high = {[192:255]};<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endgroup<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">You can create an instance:<\/span><\/p><p><span style=\"font-weight: 400;\">bus_cg cg = new();<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The purpose is not merely to prove that the signal changed. Functional coverage should represent meaningful scenarios derived from the verification plan.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if a bus protocol has different operating modes, you may want to cover combinations of those modes rather than simply measuring whether each signal toggled.<\/span><\/p><p><span style=\"font-weight: 400;\">SystemVerilog <\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/functional-coverage-vs-code-coverage\/\"><span style=\"font-weight: 400;\">functional coverage<\/span><\/a><span style=\"font-weight: 400;\"> uses constructs such as covergroups, coverpoints and bins to describe functional scenarios.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">11. Write a FIFO status condition<\/span><\/h3><p><span style=\"font-weight: 400;\">An interviewer may give you a small FIFO problem and ask you to write the empty\/full logic.<\/span><\/p><p><span style=\"font-weight: 400;\">For a simple counter-based FIFO, the conceptual conditions might be:<\/span><\/p><p><span style=\"font-weight: 400;\">assign empty = (count == 0);<\/span><\/p><p><span style=\"font-weight: 400;\">assign full\u00a0 = (count == DEPTH);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The interviewer may then change the requirement:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Can read and write happen in the same cycle?&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">That changes the design considerations.<\/span><\/p><p><span style=\"font-weight: 400;\">You need to determine:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What happens when the FIFO is empty?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Can a read and write occur simultaneously?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What happens when it is full?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Does a simultaneous read\/write maintain the same occupancy?<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">What should happen to <\/span><span style=\"font-weight: 400;\">count<\/span><span style=\"font-weight: 400;\">?<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example:<\/span><\/p><p><span style=\"font-weight: 400;\">always_ff @(posedge clk) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0case ({wr_en, rd_en})<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b10: count &lt;= count + 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02&#8217;b01: count &lt;= count &#8211; 1&#8217;b1;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default: count &lt;= count;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0endcase<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">This is a useful interview exercise because the candidate has to think about <\/span><b>boundary conditions and simultaneous events<\/b><span style=\"font-weight: 400;\">, not just syntax.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">12. Find the bug in this randomization code<\/span><\/h3><p><span style=\"font-weight: 400;\">Consider:<\/span><\/p><p><span style=\"font-weight: 400;\">class packet;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0rand bit [7:0] length;<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0constraint c_length {<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0length &gt; 10;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0length &lt; 5;<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0}<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">endclass<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The constraints are contradictory.<\/span><\/p><p><span style=\"font-weight: 400;\">There is no value that is simultaneously greater than 10 and less than 5.<\/span><\/p><p><span style=\"font-weight: 400;\">Therefore:<\/span><\/p><p><span style=\"font-weight: 400;\">packet p = new();<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">if (!p.randomize())<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0$display(&#8220;Randomization failed&#8221;);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">is an important pattern to understand.<\/span><\/p><p><span style=\"font-weight: 400;\">An interviewer may then ask:<\/span><\/p><p><b>How would you debug a randomization failure?<\/b><\/p><p><span style=\"font-weight: 400;\">Start by checking:<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Whether constraints are contradictory.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Whether a constraint is unintentionally too restrictive.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Whether <\/span><span style=\"font-weight: 400;\">rand<\/span><span style=\"font-weight: 400;\"> variables are declared correctly.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Whether <\/span><span style=\"font-weight: 400;\">randomize()<\/span><span style=\"font-weight: 400;\"> is returning failure.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Whether inline constraints conflict with class constraints.<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">This type of question tests debugging ability, not just SystemVerilog syntax.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">13. What is the difference between a dynamic array, queue and associative array?<\/span><\/h3><p><span style=\"font-weight: 400;\">This is a popular SystemVerilog coding discussion because all three are useful but serve different purposes.<\/span><\/p><h5><span style=\"font-weight: 400;\">Dynamic array<\/span><\/h5><p><span style=\"font-weight: 400;\">int data[];<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Its size can be allocated dynamically.<\/span><\/p><p><span style=\"font-weight: 400;\">data = new[10];<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Queue<\/span><\/h5><p><span style=\"font-weight: 400;\">int q[$];<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Queues support operations such as adding and removing elements.<\/span><\/p><p><span style=\"font-weight: 400;\">q.push_back(10);<\/span><\/p><p><span style=\"font-weight: 400;\">q.push_front(20);<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">int value;<\/span><\/p><p><span style=\"font-weight: 400;\">value = q.pop_front();<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Associative array<\/span><\/h5><p><span style=\"font-weight: 400;\">int memory[int];<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">The array is indexed by a key, which can be useful for sparse data structures.<\/span><\/p><p><span style=\"font-weight: 400;\">The interviewer may ask:<\/span><\/p><p><b>Which one would you use for a transaction FIFO?<\/b><\/p><p><span style=\"font-weight: 400;\">A queue is often a natural choice because transactions can be inserted and removed in order.<\/span><\/p><p><span style=\"font-weight: 400;\">The correct answer, however, depends on the actual data structure and access requirements.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">14. Write a simple scoreboard comparison<\/span><\/h3><p><span style=\"font-weight: 400;\">For a basic verification environment, an interviewer may ask how you would compare expected and actual data.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified example is:<\/span><\/p><p><span style=\"font-weight: 400;\">if (actual_data !== expected_data) begin<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0$error(&#8220;Mismatch: expected=%0h actual=%0h&#8221;,<\/span><\/p><p><span style=\"font-weight: 400;\">\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0expected_data, actual_data);<\/span><\/p><p><span style=\"font-weight: 400;\">end<\/span><\/p><p>\u00a0<\/p><p><span style=\"font-weight: 400;\">Notice the use of <\/span><span style=\"font-weight: 400;\">!==<\/span><span style=\"font-weight: 400;\"> rather than <\/span><span style=\"font-weight: 400;\">!=<\/span><span style=\"font-weight: 400;\">.<\/span><\/p><p><span style=\"font-weight: 400;\">Four-state simulation includes <\/span><span style=\"font-weight: 400;\">X<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">Z<\/span><span style=\"font-weight: 400;\">, so case inequality can be useful when you want unknown values to participate in the comparison rather than being treated like ordinary two-state values.<\/span><\/p><p><span style=\"font-weight: 400;\">A follow-up question could be:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;Why might <\/span><span style=\"font-weight: 400;\">==<\/span><span style=\"font-weight: 400;\"> produce unexpected behavior when X values are present?&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">You should be able to explain the difference between logical equality and case equality in four-state simulation.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">15. What SystemVerilog coding mistakes should you look for before submitting your solution?<\/span><\/h3><p><span style=\"font-weight: 400;\">After completing an interview coding problem, do not immediately say, &#8220;Done.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">Take a few seconds to review your code.<\/span><\/p><p><span style=\"font-weight: 400;\">Check:<\/span><\/p><h5><span style=\"font-weight: 400;\">1. Assignment type<\/span><\/h5><p><span style=\"font-weight: 400;\">Did you use blocking and nonblocking assignments appropriately?<\/span><\/p><h5><span style=\"font-weight: 400;\">2. Reset behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Does the reset meet the stated requirement?<\/span><\/p><h5><span style=\"font-weight: 400;\">3. Combinational completeness<\/span><\/h5><p><span style=\"font-weight: 400;\">Did you assign outputs in every relevant condition?<\/span><\/p><h5><span style=\"font-weight: 400;\">4. Widths<\/span><\/h5><p><span style=\"font-weight: 400;\">Could an arithmetic operation overflow or truncate unexpectedly?<\/span><\/p><h5><span style=\"font-weight: 400;\">5. Boundary conditions<\/span><\/h5><p><span style=\"font-weight: 400;\">What happens at zero, maximum value, empty, full, or simultaneous operations?<\/span><\/p><h5><span style=\"font-weight: 400;\">6. Synthesizability<\/span><\/h5><p><span style=\"font-weight: 400;\">Does the RTL describe hardware that can actually be synthesized?<\/span><\/p><h5><span style=\"font-weight: 400;\">7. Simulation behavior<\/span><\/h5><p><span style=\"font-weight: 400;\">Could race conditions, unknown values, or scheduling semantics affect the result?<\/span><\/p><h5><span style=\"font-weight: 400;\">8. Scalability<\/span><\/h5><p><span style=\"font-weight: 400;\">Could the code be parameterized or simplified without making it harder to understand?<\/span><\/p><p><span style=\"font-weight: 400;\">These checks are consistent with practical RTL interview preparation guidance: candidates are often evaluated on reset behavior, assignment types, latch avoidance, synthesizability, corner cases, and whether they can explain the hardware created by their code.<\/span><\/p><h3><span style=\"font-weight: 400;\">How to Prepare for SystemVerilog Coding Interviews<\/span><\/h3><p><span style=\"font-weight: 400;\">The best way to prepare is to code rather than simply read SystemVerilog interview questions.<\/span><\/p><p><span style=\"font-weight: 400;\">Start with small exercises:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Flip-flop<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Counter<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Shift register<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">MUX<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Decoder<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FIFO<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Arbiter<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Then move into verification-oriented exercises:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Classes<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Randomization<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Queues<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Functional coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Basic testbench components<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For each problem, follow the same process:<\/span><\/p><p><span style=\"font-weight: 400;\">Understand the requirement \u2192 identify the hardware or verification behavior \u2192 write the simplest implementation \u2192 test corner cases \u2192 explain your code.<\/span><\/p><p><span style=\"font-weight: 400;\">For verification roles, practice writing small <\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/how-to-write-efficient-testbenches-using-systemverilog\/\"><span style=\"font-weight: 400;\">SystemVerilog testbench<\/span><\/a><span style=\"font-weight: 400;\"> components instead of memorizing UVM code. SystemVerilog testbench development commonly involves drivers, monitors, scoreboards, stimulus generation, assertions, interfaces, and coverage.<\/span><\/p><p><span style=\"font-weight: 400;\">You should also practice explaining <\/span><i><span style=\"font-weight: 400;\">why<\/span><\/i><span style=\"font-weight: 400;\"> you chose a particular construct.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if asked to write a counter, do not stop after producing the code. Explain:<\/span><\/p><p><span style=\"font-weight: 400;\">&#8220;I used <\/span><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\"> because this is clocked sequential logic, used a nonblocking assignment for the register update, and used a parameter so the counter width can be changed without rewriting the module.&#8221;<\/span><\/p><p><span style=\"font-weight: 400;\">That explanation demonstrates considerably more understanding than the code alone.<\/span><\/p><h4><span style=\"font-weight: 400;\">Final Takeaway<\/span><\/h4><p><span style=\"font-weight: 400;\">SystemVerilog coding interviews are designed to test whether you can translate a specification into correct, maintainable RTL or verification code.<\/span><\/p><p><span style=\"font-weight: 400;\">The most important areas to practice include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Sequential and combinational RTL<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">always_ff<\/span><span style=\"font-weight: 400;\"> and <\/span><span style=\"font-weight: 400;\">always_comb<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Blocking and nonblocking assignments<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">FSM implementation<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Parameterized designs<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Classes and constructors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Randomization and constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Dynamic arrays and queues<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interfaces<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assertions<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Functional coverage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scoreboards and testbench coding<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Debugging incorrect SystemVerilog<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Do not focus on writing the shortest possible solution. Focus on writing code that clearly communicates your design or verification intent.<\/span><\/p><p><span style=\"font-weight: 400;\">A strong interview candidate can write the code, explain why it works, identify its limitations, and modify it when the interviewer changes the requirement.<\/span><\/p><p><span style=\"font-weight: 400;\">That is the difference between knowing SystemVerilog syntax and being able to use SystemVerilog effectively in a VLSI engineering environment.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>SystemVerilog interviews are often more practical than candidates expect. Knowing the syntax of logic, always_ff, classes, constraints, or assertions is useful, but interviewers frequently ask candidates to write code, modify existing code, identify a bug, or explain what the code actually does. For RTL design and functional verification roles, coding questions can range from simple [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10270","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Top SystemVerilog Coding Questions for VLSI Interviews | InSkill<\/title>\n<meta name=\"description\" content=\"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Top SystemVerilog Coding Questions for VLSI Interviews | InSkill\" \/>\n<meta property=\"og:description\" content=\"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\" \/>\n<meta property=\"og:site_name\" content=\"Inskill VLSIGURU Elearning Platform\" \/>\n<meta property=\"article:published_time\" content=\"2026-10-06T10:54:22+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-10-06T11:19:52+00:00\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"11 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f\"},\"headline\":\"Top SystemVerilog Coding Questions Asked in VLSI Interviews\",\"datePublished\":\"2026-10-06T10:54:22+00:00\",\"dateModified\":\"2026-10-06T11:19:52+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\"},\"wordCount\":2382,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\/\/inskill.in\/training\/#organization\"},\"articleSection\":[\"VLSI\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\",\"url\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\",\"name\":\"Top SystemVerilog Coding Questions for VLSI Interviews | InSkill\",\"isPartOf\":{\"@id\":\"https:\/\/inskill.in\/training\/#website\"},\"datePublished\":\"2026-10-06T10:54:22+00:00\",\"dateModified\":\"2026-10-06T11:19:52+00:00\",\"description\":\"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.\",\"breadcrumb\":{\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/inskill.in\/training\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Top SystemVerilog Coding Questions Asked in VLSI Interviews\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/inskill.in\/training\/#website\",\"url\":\"https:\/\/inskill.in\/training\/\",\"name\":\"Inskill VLSIGURU Elearning Platform\",\"description\":\"Best VLSI Training Institute\",\"publisher\":{\"@id\":\"https:\/\/inskill.in\/training\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/inskill.in\/training\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/inskill.in\/training\/#organization\",\"name\":\"Inskill VLSIGURU Elearning Platform\",\"url\":\"https:\/\/inskill.in\/training\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png\",\"contentUrl\":\"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png\",\"width\":207,\"height\":89,\"caption\":\"Inskill VLSIGURU Elearning Platform\"},\"image\":{\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f\",\"name\":\"admin\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/inskill.in\/training\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g\",\"caption\":\"admin\"},\"sameAs\":[\"https:\/\/inskill.in\/training\"],\"url\":\"https:\/\/inskill.in\/training\/author\/admin\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Top SystemVerilog Coding Questions for VLSI Interviews | InSkill","description":"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/","og_locale":"en_US","og_type":"article","og_title":"Top SystemVerilog Coding Questions for VLSI Interviews | InSkill","og_description":"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.","og_url":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/","og_site_name":"Inskill VLSIGURU Elearning Platform","article_published_time":"2026-10-06T10:54:22+00:00","article_modified_time":"2026-10-06T11:19:52+00:00","author":"admin","twitter_card":"summary_large_image","twitter_misc":{"Written by":"admin","Est. reading time":"11 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#article","isPartOf":{"@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/"},"author":{"name":"admin","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f"},"headline":"Top SystemVerilog Coding Questions Asked in VLSI Interviews","datePublished":"2026-10-06T10:54:22+00:00","dateModified":"2026-10-06T11:19:52+00:00","mainEntityOfPage":{"@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/"},"wordCount":2382,"commentCount":0,"publisher":{"@id":"https:\/\/inskill.in\/training\/#organization"},"articleSection":["VLSI"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/","url":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/","name":"Top SystemVerilog Coding Questions for VLSI Interviews | InSkill","isPartOf":{"@id":"https:\/\/inskill.in\/training\/#website"},"datePublished":"2026-10-06T10:54:22+00:00","dateModified":"2026-10-06T11:19:52+00:00","description":"Prepare for VLSI interviews with practical SystemVerilog coding questions covering RTL, FSMs, constraints, classes, assertions, coverage, interfaces, and testbenches.","breadcrumb":{"@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/inskill.in\/training\/vlsi\/top-systemverilog-coding-questions-vlsi-interviews\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/inskill.in\/training\/"},{"@type":"ListItem","position":2,"name":"Top SystemVerilog Coding Questions Asked in VLSI Interviews"}]},{"@type":"WebSite","@id":"https:\/\/inskill.in\/training\/#website","url":"https:\/\/inskill.in\/training\/","name":"Inskill VLSIGURU Elearning Platform","description":"Best VLSI Training Institute","publisher":{"@id":"https:\/\/inskill.in\/training\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/inskill.in\/training\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/inskill.in\/training\/#organization","name":"Inskill VLSIGURU Elearning Platform","url":"https:\/\/inskill.in\/training\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/","url":"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png","contentUrl":"https:\/\/inskill.in\/training\/wp-content\/uploads\/2025\/01\/inskill-2.png","width":207,"height":89,"caption":"Inskill VLSIGURU Elearning Platform"},"image":{"@id":"https:\/\/inskill.in\/training\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/9abb65edd31606e6675ad9c153f2d42f","name":"admin","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/inskill.in\/training\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/ae1b84b5e32e75453917297a43292af55fcc34a59a0d20dc5403287472a37c28?s=96&d=mm&r=g","caption":"admin"},"sameAs":["https:\/\/inskill.in\/training"],"url":"https:\/\/inskill.in\/training\/author\/admin\/"}]}},"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10270","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/comments?post=10270"}],"version-history":[{"count":4,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10270\/revisions"}],"predecessor-version":[{"id":10276,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/posts\/10270\/revisions\/10276"}],"wp:attachment":[{"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/media?parent=10270"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/categories?post=10270"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/inskill.in\/training\/wp-json\/wp\/v2\/tags?post=10270"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}