{"id":10306,"date":"2026-10-14T06:55:42","date_gmt":"2026-10-14T06:55:42","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=10306"},"modified":"2026-10-14T06:57:06","modified_gmt":"2026-10-14T06:57:06","slug":"dft-interview-questions-scan-atpg","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/dft-interview-questions-scan-atpg\/","title":{"rendered":"DFT Interview Questions on Scan and ATPG"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"10306\" class=\"elementor elementor-10306\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-ffb5dac elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"ffb5dac\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-da50cb6\" data-id=\"da50cb6\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-c420338 elementor-widget elementor-widget-text-editor\" data-id=\"c420338\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">Design for Testability (DFT) is an essential part of the VLSI design flow because a chip must not only function correctly but also be testable after manufacturing. DFT engineers design structures that help detect manufacturing defects, evaluate fault coverage, and improve the efficiency of production testing.<\/span><\/p><p><span style=\"font-weight: 400;\">For freshers preparing for DFT Engineer, ASIC Design, or Test Engineering roles, <\/span><b>scan and Automatic Test Pattern Generation (ATPG)<\/b><span style=\"font-weight: 400;\"> are particularly important interview topics. Interviewers commonly ask about scan-chain operation, fault models, stuck-at faults, transition faults, test coverage, and debugging failed patterns.<\/span><\/p><p><span style=\"font-weight: 400;\">This guide explains the most important DFT interview questions on scan and ATPG, with practical examples and scenario-based answers.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Design for Testability (DFT)?<\/span><\/h3><p><span style=\"font-weight: 400;\">Design for Testability is a collection of design techniques that make it easier to detect manufacturing defects in integrated circuits. DFT structures are incorporated during the design process to improve access to internal logic during testing.<\/span><\/p><p><span style=\"font-weight: 400;\">Without DFT, internal states in a complex sequential circuit may be difficult to control and observe through primary inputs and outputs alone.<\/span><\/p><p><span style=\"font-weight: 400;\">Common DFT techniques include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scan-chain insertion<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Automatic Test Pattern Generation (ATPG)<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scan compression<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Boundary scan using JTAG<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory Built-In Self-Test (MBIST)<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Logic Built-In Self-Test (LBIST)<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example, a logic gate may be physically defective even though the RTL design is functionally correct. DFT structures and test patterns help expose such defects after fabrication.<\/span><\/p><p><span style=\"font-weight: 400;\">Read this<\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/introduction-to-dft-making-chips-testable\/\"> <span style=\"font-weight: 400;\">introduction to DFT and chip testability<\/span><\/a><span style=\"font-weight: 400;\"> for a broader overview of the role of DFT in the semiconductor development flow.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a Scan Chain, and Why Is It Required?<\/span><\/h3><p><span style=\"font-weight: 400;\">A scan chain is a serial connection of scan-enabled flip-flops that allows internal sequential states to be loaded and observed during test mode.<\/span><\/p><p><span style=\"font-weight: 400;\">In normal functional operation, a flip-flop captures data from its functional input. In scan mode, a scan flip-flop selects its scan input and shifts test data from one scan cell to the next.<\/span><\/p><p><span style=\"font-weight: 400;\">A typical scan cell provides a functional data input, scan input, scan output, and scan-enable control.<\/span><\/p><p><span style=\"font-weight: 400;\">Scan improves two important properties:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Controllability:<\/b><span style=\"font-weight: 400;\"> The ability to set internal states to required values.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Observability:<\/b><span style=\"font-weight: 400;\"> The ability to observe internal states or their effects at accessible outputs.<\/span><\/li><\/ul><p><b>Practical example:<\/b><span style=\"font-weight: 400;\"> Imagine a block containing 100 flip-flops. Without scan access, reaching a particular internal state might require a complex sequence of functional input patterns. With scan, test data can be shifted directly into the scan cells, making internal states much easier to control.<\/span><\/p><p><span style=\"font-weight: 400;\">Scan chains are therefore central to structural testing of many digital ASICs.<\/span><\/p><h3><span style=\"font-weight: 400;\">How Does Scan Testing Work?<\/span><\/h3><p><span style=\"font-weight: 400;\">Scan testing generally involves three phases: shift-in, capture, and shift-out.<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Shift-in:<\/b><span style=\"font-weight: 400;\"> Test data is shifted into the scan chains.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Capture:<\/b><span style=\"font-weight: 400;\"> The circuit evaluates the applied test conditions, and the response is captured in scan cells.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Shift-out:<\/b><span style=\"font-weight: 400;\"> Captured data is shifted out and compared with the expected response.<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">For a simple example, consider three scan flip-flops connected as follows:<\/span><\/p><p><span style=\"font-weight: 400;\">Scan In \u2192 FF1 \u2192 FF2 \u2192 FF3 \u2192 Scan Out<\/span><\/p><p><span style=\"font-weight: 400;\">When scan enable is active, a test sequence is shifted through the chain. After the required data is loaded, the design performs the appropriate capture operation. The resulting values are then shifted out for comparison.<\/span><\/p><p><span style=\"font-weight: 400;\">The exact procedure depends on the test pattern type and the scan architecture.<\/span><\/p><p><b>Interview tip:<\/b><span style=\"font-weight: 400;\"> Do not describe scan testing as only shifting data through flip-flops. Explain that shifting establishes the test state, capture evaluates the circuit response, and shifting out enables response comparison.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Scan Insertion?<\/span><\/h3><p><span style=\"font-weight: 400;\">Scan insertion is the process of replacing eligible functional flip-flops with scan-capable cells and connecting them into scan chains.<\/span><\/p><p><span style=\"font-weight: 400;\">A typical scan insertion flow includes:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reviewing the design and DFT requirements.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Checking test clocks, resets, and scan-enable signals.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Running DFT design-rule checks.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Replacing suitable sequential cells with scan cells.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Connecting scan chains.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Validating chain connectivity and test operation.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Generating the required test information for ATPG.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Scan insertion can introduce additional cell area and routing requirements. It can also affect timing, particularly when scan cells have different characteristics from the original flip-flops.<\/span><\/p><p><span style=\"font-weight: 400;\">A practical DFT engineer must therefore check both testability and implementation constraints. Learn more about<\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/why-scan-insertion-is-critical-vlsi\/\"> <span style=\"font-weight: 400;\">why scan insertion is critical in the VLSI flow<\/span><\/a><span style=\"font-weight: 400;\">.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is ATPG?<\/span><\/h3><p><span style=\"font-weight: 400;\">Automatic Test Pattern Generation is the process of generating test patterns that detect specified faults in a circuit model.<\/span><\/p><p><span style=\"font-weight: 400;\">ATPG tools analyze the design structure and fault models to determine input conditions that activate a fault and make its effect observable at a primary output or scan-captured response.<\/span><\/p><p><span style=\"font-weight: 400;\">For a fault to be detected, the test generally needs to:<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Activate the fault by setting the relevant signal to a value that exposes the difference between the good and faulty circuits.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Propagate the fault effect through the logic.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Make the effect observable at an accessible output or scan point.<\/span><\/li><\/ol><p><b>Example:<\/b><span style=\"font-weight: 400;\"> Suppose an AND gate implements Y=A\u2227BY=A\\land B, and its output is modeled as stuck-at-0. Applying A=1A=1 and B=1B=1 should produce Y=1Y=1 in the fault-free circuit. The faulty circuit produces Y=0Y=0, so the fault effect can be observed if the output is accessible.<\/span><\/p><p><span style=\"font-weight: 400;\">This simplified example illustrates fault activation and observation. Real ATPG also considers the surrounding circuit, constraints, and fault propagation paths.<\/span><\/p><p><span style=\"font-weight: 400;\">For a deeper explanation, read<\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/how-atpg-works-fault-detection\/\"> <span style=\"font-weight: 400;\">how ATPG works to detect modeled faults<\/span><\/a><span style=\"font-weight: 400;\">.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is a Stuck-at Fault?<\/span><\/h3><p><span style=\"font-weight: 400;\">A stuck-at fault models a signal that behaves as though it is permanently fixed at logic 0 or logic 1, regardless of the value that should be present.<\/span><\/p><p><span style=\"font-weight: 400;\">The two common types are:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Stuck-at-0 (SA0):<\/b><span style=\"font-weight: 400;\"> The signal behaves as though it is always 0.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Stuck-at-1 (SA1):<\/b><span style=\"font-weight: 400;\"> The signal behaves as though it is always 1.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Consider a signal XX that should become 1 under a particular test condition. If the signal has an SA0 fault, the faulty circuit produces 0 instead.<\/span><\/p><p><span style=\"font-weight: 400;\">To detect an SA0 fault, a test must attempt to drive the fault site to 1 and propagate the resulting discrepancy to an observable point. To detect an SA1 fault, the test must attempt to drive the site to 0 and propagate the discrepancy.<\/span><\/p><p><b>Common interview follow-up:<\/b><span style=\"font-weight: 400;\"> Are stuck-at faults identical to physical defects? No. They are abstract fault models used to represent certain defect behaviors. A physical manufacturing defect can have more complex effects than a simple stuck-at condition.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is the Difference Between Stuck-at and Transition Faults?<\/span><\/h3><p><span style=\"font-weight: 400;\">Stuck-at faults model a signal that is permanently fixed at a logic value. Transition faults model a signal transition that is too slow to meet the required timing.<\/span><\/p><p><span style=\"font-weight: 400;\">Transition fault testing considers two cases:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Slow-to-rise:<\/b><span style=\"font-weight: 400;\"> A 0-to-1 transition occurs too slowly.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Slow-to-fall:<\/b><span style=\"font-weight: 400;\"> A 1-to-0 transition occurs too slowly.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">For example, a signal may eventually reach logic 1 but arrive too late for the receiving register to capture it correctly at the intended clock edge. A static stuck-at test may not expose this timing-related defect, whereas an at-speed transition test may detect it.<\/span><\/p><p><span style=\"font-weight: 400;\">Transition testing generally requires suitable launch and capture conditions and appropriate clocking support.<\/span><\/p><p><span style=\"font-weight: 400;\">A useful interview answer distinguishes the purpose of each model: stuck-at testing targets static logical faults, while transition testing targets delay-related behavior at a signal transition.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Fault Coverage in ATPG?<\/span><\/h3><p><span style=\"font-weight: 400;\">Fault coverage measures how effectively generated test patterns detect the faults considered by a specified fault model and analysis.<\/span><\/p><p><span style=\"font-weight: 400;\">A simplified definition is:<\/span><\/p><p><span style=\"font-weight: 400;\">Fault Coverage=Detected FaultsTotal Testable Faults\u00d7100%\\text{Fault Coverage}= \\frac{\\text{Detected Faults}}{\\text{Total Testable Faults}}\\times100\\%<\/span><\/p><p><span style=\"font-weight: 400;\">The denominator and treatment of fault categories can vary by tool and reporting methodology. Some reports distinguish detected, undetected, untestable, aborted, and unclassified faults. Always check the report definition before interpreting a coverage percentage.<\/span><\/p><p><b>Example:<\/b><span style=\"font-weight: 400;\"> If 900 faults are detected out of 1,000 faults included in a simplified coverage calculation, the coverage is 90%.<\/span><\/p><p><span style=\"font-weight: 400;\">A high coverage percentage is important, but it does not automatically mean every possible physical defect will be detected. Coverage depends on the fault model, design constraints, test architecture, and pattern quality.<\/span><\/p><p><span style=\"font-weight: 400;\">For additional practice, review<\/span><a href=\"https:\/\/inskill.in\/training\/vlsi\/how-to-achieve-higher-fault-coverage-in-atpg\/\"> <span style=\"font-weight: 400;\">methods for improving ATPG fault coverage<\/span><\/a><span style=\"font-weight: 400;\">.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is the Difference Between Fault Coverage and Test Coverage?<\/span><\/h3><p><span style=\"font-weight: 400;\">Fault coverage is associated with the detection of modeled faults during structural testing. Test coverage is a broader term whose meaning depends on the context and metric being discussed.<\/span><\/p><p><span style=\"font-weight: 400;\">In functional verification, coverage may refer to exercised features, scenarios, or code structures. In DFT, engineers often focus on fault coverage, pattern effectiveness, and the status of modeled faults.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a functional testbench might achieve high functional coverage while the manufactured circuit still contains defects that its tests cannot expose. Conversely, ATPG can target structural faults without proving that every functional requirement has been verified.<\/span><\/p><p><b>Interview tip:<\/b><span style=\"font-weight: 400;\"> Clarify which coverage metric is being discussed instead of treating all forms of coverage as interchangeable.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Scan Chain Testing, and Why Can a Scan Chain Fail?<\/span><\/h3><p><span style=\"font-weight: 400;\">Scan-chain testing checks whether scan cells are connected and operating as intended. Problems can arise from incorrect connectivity, unsuitable scan controls, clock issues, reset behavior, or scan-cell implementation errors.<\/span><\/p><p><span style=\"font-weight: 400;\">Possible symptoms include:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Incorrect shifted-out data.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A chain that stops shifting at a particular point.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unexpected values in scan cells.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Chain-length or connectivity mismatches.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scan tests that fail even when the expected functional behavior is correct.<\/span><\/li><\/ul><p><b>Practical scenario:<\/b><span style=\"font-weight: 400;\"> A scan chain is expected to contain 200 cells, but the observed shift sequence does not match the expected pattern. A DFT engineer should check the chain definition, scan-in and scan-out connectivity, scan enable, clock behavior, and any reset conditions that affect the cells.<\/span><\/p><p><span style=\"font-weight: 400;\">Do not immediately assume that the scan cells are defective. A test configuration or connectivity problem can produce similar symptoms.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is Scan Compression?<\/span><\/h3><p><span style=\"font-weight: 400;\">Scan compression reduces the amount of external test data and can reduce tester memory requirements and test application time.<\/span><\/p><p><span style=\"font-weight: 400;\">A typical compressed scan architecture uses on-chip decompression logic to distribute test data to internal scan chains and compaction logic to combine responses for observation.<\/span><\/p><p><span style=\"font-weight: 400;\">Compression allows a design to support many internal scan chains without requiring an equivalent number of external tester channels.<\/span><\/p><p><span style=\"font-weight: 400;\">However, compression introduces additional considerations, including unknown-value propagation, response masking, diagnosis complexity, and possible coverage changes.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, a design may contain many internal scan chains but only a limited number of external scan channels. A compression architecture helps deliver test data to those chains efficiently, subject to the design&#8217;s compression scheme and constraints.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is ATPG DRC, and Why Is It Important?<\/span><\/h3><p><span style=\"font-weight: 400;\">ATPG design-rule checking (DRC) identifies conditions in the design or test setup that may prevent correct test generation or application.<\/span><\/p><p><span style=\"font-weight: 400;\">Depending on the tool and flow, checks may involve scan-chain connectivity, clocks, resets, controllability, test-mode configuration, and other structural or procedural requirements.<\/span><\/p><p><span style=\"font-weight: 400;\">If ATPG DRC reports an issue, the engineer should understand the specific rule, locate the affected logic or constraint, and correct the underlying problem before generating or relying on patterns.<\/span><\/p><p><b>Example:<\/b><span style=\"font-weight: 400;\"> If a required test clock is not defined correctly, ATPG may be unable to generate valid patterns for sequential elements controlled by that clock. Correcting the clock setup and rerunning the relevant checks is more appropriate than attempting to improve fault coverage without resolving the configuration issue.<\/span><\/p><h3><span style=\"font-weight: 400;\">Why Can ATPG Fault Coverage Be Low?<\/span><\/h3><p><span style=\"font-weight: 400;\">Low fault coverage can result from several conditions:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Some faults are untestable under the current constraints.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Fault effects cannot be propagated to an observable point.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Test clocks or resets are constrained incorrectly.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Scan chains contain structural or connectivity problems.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Unknown values interfere with pattern generation or response comparison.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">ATPG encounters difficult faults or reaches resource limits.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Test points or other testability structures may be needed.<\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">A systematic investigation begins with the fault report. Separate untestable faults from aborted or undetected faults, and investigate the reasons reported by the tool.<\/span><\/p><p><span style=\"font-weight: 400;\">For example, if a group of faults remains undetected because a control signal cannot be set to the required value in test mode, the issue may be limited controllability rather than an ATPG algorithm failure.<\/span><\/p><p><span style=\"font-weight: 400;\">Potential remedies include correcting constraints, improving test access, adding suitable test points, or revisiting the test architecture. Each change should be validated against design behavior and implementation requirements.<\/span><\/p><h3><span style=\"font-weight: 400;\">What Is ATPG Pattern Simulation, and Why Is It Required?<\/span><\/h3><p><span style=\"font-weight: 400;\">ATPG pattern simulation checks whether generated patterns produce the expected responses when applied to the relevant design model.<\/span><\/p><p><span style=\"font-weight: 400;\">Simulation helps detect problems such as incorrect pattern application, scan connectivity issues, unexpected unknown values, and mismatches between expected and simulated responses.<\/span><\/p><p><b>Practical scenario:<\/b><span style=\"font-weight: 400;\"> ATPG generates a pattern, but gate-level simulation produces an unexpected value at the scan output. The engineer should check the failing cycle, scan-chain connectivity, clock and reset sequencing, test-mode signals, and the source of any unknown values.<\/span><\/p><p><span style=\"font-weight: 400;\">A mismatch does not automatically prove that the pattern generator is wrong. It may indicate a design, constraint, modeling, or testbench problem.<\/span><\/p><p><span style=\"font-weight: 400;\">The goal is to identify the cause, correct it, and rerun the required validation.<\/span><\/p><h3><span style=\"font-weight: 400;\">Scenario-Based Interview Question: How Would You Improve ATPG Coverage?<\/span><\/h3><p><span style=\"font-weight: 400;\">Start by examining the fault summary and identifying the categories responsible for the coverage shortfall. Check whether faults are undetected, untestable, aborted, or affected by configuration issues.<\/span><\/p><p><span style=\"font-weight: 400;\">Next, inspect representative failing faults and determine whether the problem involves controllability, observability, clocking, scan access, unknown values, or resource limits.<\/span><\/p><p><span style=\"font-weight: 400;\">Depending on the findings, possible actions include:<\/span><\/p><ol><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Correcting test constraints or test-mode configuration.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Fixing scan-chain or DFT rule violations.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Improving observability or controllability through appropriate test structures.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reviewing X-handling and response-masking settings.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Evaluating additional patterns or supported ATPG options.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Rerunning fault simulation and reviewing the updated reports.<\/span><\/li><\/ol><p><span style=\"font-weight: 400;\">A strong answer emphasizes evidence-based debugging. Adding more patterns alone may not solve a coverage issue caused by an incorrectly constrained signal or a structural testability problem.<\/span><\/p><h3><span style=\"font-weight: 400;\">How Should Freshers Prepare for Scan and ATPG Interviews?<\/span><\/h3><p><span style=\"font-weight: 400;\">Freshers should first understand scan-chain operation, scan insertion, controllability, observability, stuck-at faults, transition faults, and fault coverage. They should then practise explaining how ATPG activates faults and propagates their effects to observable points.<\/span><\/p><p><span style=\"font-weight: 400;\">Review common DFT reports and learn to explain what you would investigate when scan chains fail, ATPG DRC reports errors, or fault coverage is lower than expected.<\/span><\/p><p><span style=\"font-weight: 400;\">For structured preparation, explore the<\/span><a href=\"https:\/\/vlsiguru.com\/interview-preparation-courses\/dft-interview-preparation\"> <span style=\"font-weight: 400;\">DFT Interview Preparation course at VLSIGuru<\/span><\/a><span style=\"font-weight: 400;\"> and the<\/span><a href=\"https:\/\/inskill.in\/training\/dft-interview-preparation-training\/\"> <span style=\"font-weight: 400;\">DFT Interview Preparation Training at InSkill<\/span><\/a><span style=\"font-weight: 400;\">. These resources cover scan insertion, ATPG, fault models, coverage analysis, simulation debugging, and related interview topics.<\/span><\/p><p><span style=\"font-weight: 400;\">If you have completed a DFT project, prepare to explain the flow you followed, the reports you examined, one problem you investigated, and how you validated the result. If you have not used commercial DFT tools, clearly distinguish conceptual examples from hands-on experience.<\/span><\/p><h4><span style=\"font-weight: 400;\">Conclusion<\/span><\/h4><p><span style=\"font-weight: 400;\">Scan and ATPG are core topics for DFT interviews because they connect circuit structure with manufacturing test. Candidates should be able to explain how scan chains improve controllability and observability, how ATPG detects modeled faults, and how fault coverage is interpreted.<\/span><\/p><p><span style=\"font-weight: 400;\">Practise the scenario-based questions as carefully as the definitions. When a scan chain fails or ATPG coverage drops, explain how you would inspect the reports, isolate the cause, and verify the fix. This approach demonstrates practical understanding rather than memorization alone.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Design for Testability (DFT) is an essential part of the VLSI design flow because a chip must not only function correctly but also be testable after manufacturing. DFT engineers design structures that help detect manufacturing defects, evaluate fault coverage, and improve the efficiency of production testing. For freshers preparing for DFT Engineer, ASIC Design, or [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-10306","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>DFT Interview Questions on Scan and ATPG<\/title>\n<meta name=\"description\" content=\"Prepare for DFT interviews with scan and ATPG questions covering scan chains, stuck-at faults, transition faults, fault coverage, scan insertion, and debugging.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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