{"id":9043,"date":"2026-02-09T12:10:14","date_gmt":"2026-02-09T12:10:14","guid":{"rendered":"https:\/\/inskill.in\/training\/?p=9043"},"modified":"2026-02-09T12:10:22","modified_gmt":"2026-02-09T12:10:22","slug":"what-happens-after-rtl","status":"publish","type":"post","link":"https:\/\/inskill.in\/training\/vlsi\/what-happens-after-rtl\/","title":{"rendered":"What Happens After RTL: A Deep Dive into Physical Design Flow"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"9043\" class=\"elementor elementor-9043\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-0be9848 elementor-section-boxed elementor-section-height-default elementor-section-height-default wpr-particle-no wpr-jarallax-no wpr-parallax-no wpr-sticky-section-no\" data-id=\"0be9848\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-7564d29\" data-id=\"7564d29\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e95200a elementor-widget elementor-widget-text-editor\" data-id=\"e95200a\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.11.2 - 22-02-2023 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><span style=\"font-weight: 400;\">In modern VLSI chip design, the journey doesn\u2019t stop at writing RTL. In fact, the RTL (Register Transfer Level) representation is just the beginning. It\u2019s a high-level functional model that describes <\/span><i><span style=\"font-weight: 400;\">what<\/span><\/i><span style=\"font-weight: 400;\"> a design should do, not <\/span><i><span style=\"font-weight: 400;\">how<\/span><\/i><span style=\"font-weight: 400;\"> it will be physically implemented on silicon. That transformation from abstract logic to a manufacturable silicon layout is handled by the Physical Design Flow, a critical stage in ASIC and FPGA development.<\/span><\/p><p><span style=\"font-weight: 400;\">In this blog, we break down what happens after RTL, exploring every major step in the physical design flow, from synthesis to GDSII, while explaining key concepts, tools, challenges, and best practices. Whether you\u2019re an aspiring VLSI engineer, student, or professional bridging the gap between RTL and silicon, this guide will give you a solid grasp of the journey ahead.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">1. RTL Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">Before diving into physical design, RTL must be thoroughly verified to ensure correctness. This isn\u2019t technically in the physical design flow, but it\u2019s a <\/span><i><span style=\"font-weight: 400;\">gate check<\/span><\/i><span style=\"font-weight: 400;\"> because physical implementation depends on verified logic.<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Functional simulation<\/b><span style=\"font-weight: 400;\">: Running testbenches against RTL.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Code coverage &amp; assertion checks<\/b><span style=\"font-weight: 400;\">: Ensuring all scenarios are exercised.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Formal verification<\/b><span style=\"font-weight: 400;\">: Proving functional equivalence in some cases.<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Only after verification, confidence is high, do we proceed to the next stage,\u00a0 <\/span><i><span style=\"font-weight: 400;\">logic synthesis<\/span><\/i><span style=\"font-weight: 400;\">.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">2. Logic Synthesis<\/span><\/h3><p><span style=\"font-weight: 400;\">Once RTL is verified, it is synthesized into a gate-level netlist with the help of synthesis tools such as Synopsys Design Compiler or Cadence Genus.<\/span><\/p><h5><span style=\"font-weight: 400;\">Purpose<\/span><\/h5><p><span style=\"font-weight: 400;\">Transform high-level behavioral descriptions (Verilog\/VHDL) into a structural representation built from standard cell libraries.<\/span><\/p><h5><span style=\"font-weight: 400;\">Key Tasks<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Technology mapping<\/b><span style=\"font-weight: 400;\">: Translating RTL constructs into specific logic cells (AND, OR, flip-flops) available in the target library.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Optimization<\/b><span style=\"font-weight: 400;\">: Balancing between area, timing, and power based on constraints provided by the designer.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Constraint enforcement<\/b><span style=\"font-weight: 400;\">: Applying timing, power and area constraints via Synopsys SDC format.<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Output<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A gate-level netlist (.v or .edf file)<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Reports on area, timing and power<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Constraint files that feed into physical design<\/span><\/li><\/ul><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">3. Floorplanning<\/span><\/h3><p><span style=\"font-weight: 400;\">Floorplanning is the stage where designers decide <\/span><i><span style=\"font-weight: 400;\">how<\/span><\/i><span style=\"font-weight: 400;\"> to physically arrange logic blocks on the chip.<\/span><\/p><h5><span style=\"font-weight: 400;\">Why It Matters<\/span><\/h5><p><span style=\"font-weight: 400;\">A good floorplan reduces interconnect congestion, improves timing, and simplifies placement and routing later in the flow.<\/span><\/p><h5><span style=\"font-weight: 400;\">Tasks in Floorplanning<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Defining core area<\/b><span style=\"font-weight: 400;\">: The usable area inside the chip\u2019s bounding box.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Macro placement<\/b><span style=\"font-weight: 400;\">: Placing large blocks like memories and DSP blocks.<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Aspect ratio &amp; power planning<\/b><span style=\"font-weight: 400;\">: Allocating regions for power grids and I\/O pads.<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Deliverables<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">A floorplan layout<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power distribution network plan (PDN)<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Block placement guideline<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h3><span style=\"font-weight: 400;\">4. Placement<\/span><\/h3><p><span style=\"font-weight: 400;\">After floorplanning, the gate-level netlist moves to placement, where each standard cell is assigned a physical location.<\/span><\/p><h5><span style=\"font-weight: 400;\">Objectives<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimize total wire length<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Achieve timing closure<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Respect design rules<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Important Steps<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Global placement<\/b><span style=\"font-weight: 400;\">: Rough positioning of cells in rows<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Legalization<\/b><span style=\"font-weight: 400;\">: Adjusting to legal positions without overlap<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Detailed placement<\/b><span style=\"font-weight: 400;\">: Final refinement<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Placement tools (e.g., Cadence Innovus, Synopsys ICC2) use heuristics to optimize <\/span><i><span style=\"font-weight: 400;\">timing, power,<\/span><\/i><span style=\"font-weight: 400;\"> and <\/span><i><span style=\"font-weight: 400;\">area<\/span><\/i><span style=\"font-weight: 400;\"> simultaneously.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">5. Clock Tree Synthesis (CTS)<\/span><\/h3><p><span style=\"font-weight: 400;\">Clocks drive synchronous design. But after placement, clocks still need careful routing to ensure all flip-flops receive the clock simultaneously.<\/span><\/p><h5><span style=\"font-weight: 400;\">What CTS Does<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Builds a balanced clock tree<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimizes clock skew (difference in arrival time between endpoints)<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Controls clock insertion delay<\/span><b><br \/><br \/><\/b><\/li><\/ul><h5><span style=\"font-weight: 400;\">Challenges<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Balancing skew versus latency<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power impact of clock buffers<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Managing multiple clock domains<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Proper CTS ensures the design meets timing across all corners.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">6. Routing<\/span><\/h3><p><span style=\"font-weight: 400;\">With placement and clocks in place, it\u2019s time to route, i.e., lay down the actual metal wires that connect every cell pin.<\/span><\/p><h5><span style=\"font-weight: 400;\">Types of Routing<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Global routing<\/b><span style=\"font-weight: 400;\">: Determines routes at a high level<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Detailed routing<\/b><span style=\"font-weight: 400;\">: Assigns exact tracks and layers<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Goals<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Respect spacing and width DRC (Design Rule Check) constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimize crosstalk and signal integrity issues<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Maintain timing targets<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Routing is perhaps the most complex step because real silicon has physical properties \u2014 resistance, capacitance, interference \u2014 that must be respected.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">7. Physical Verification<\/span><\/h3><p><span style=\"font-weight: 400;\">After routing, the design must be checked for manufacturability. Two major checks are performed:<\/span><\/p><h5><span style=\"font-weight: 400;\">Design Rule Check (DRC)<\/span><\/h5><p><span style=\"font-weight: 400;\">DRC verifies the layout against foundry design rules such as:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimum spacing<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Minimum width<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Via rules<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Metal density<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Violations here can lead to manufacturing faults.<\/span><\/p><p>\u00a0<\/p><h5><span style=\"font-weight: 400;\">Layout vs. Schematic (LVS)<\/span><\/h5><p><span style=\"font-weight: 400;\">LVS compares the layout netlist to the original gate-level netlist to ensure:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">No missing or extra connections<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Correct component representation<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Physical verification flows are done using tools like Mentor Calibre or Synopsys IC Validator.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">8. Static Timing Analysis (STA): Timing Closure<\/span><\/h3><p><span style=\"font-weight: 400;\">With layout and connections complete, the design undergoes Static Timing Analysis (STA) to check:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Setup and hold times<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Path delays through logic and interconnect<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Timing across corners (process, voltage, temperature)<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Why STA Is Essential<\/span><\/h5><p><span style=\"font-weight: 400;\">Physical delays vary due to wire resistance\/capacitance and cell characteristics. STA computes the worst-case timing paths without simulation.<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/p><h5><span style=\"font-weight: 400;\">Actions After STA<\/span><\/h5><p><span style=\"font-weight: 400;\">If paths fail timing, designers may:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Resynthesize logic<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Re-place\/re-route cells<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Adjust constraints<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Add buffers or restructure paths<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Tools such as Synopsys PrimeTime are commonly used here.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">9. Power Analysis and Optimization<\/span><\/h3><p><span style=\"font-weight: 400;\">Performance isn\u2019t the only goal, power matters!<\/span><\/p><h5><span style=\"font-weight: 400;\">Power Checks Include<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Dynamic power<\/b><span style=\"font-weight: 400;\">: Switching activity<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>Leakage power<\/b><span style=\"font-weight: 400;\">: Idle transistors<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><b>IR Drop &amp; Electromigration<\/b><span style=\"font-weight: 400;\">: Power supply integrity<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><h5><span style=\"font-weight: 400;\">Techniques<\/span><\/h5><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Clock gating<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power gating<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Multi-Vt library usage<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Late power optimization passes<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Tools like Apache RedHawk or PrimePower analyze and guide power fixes.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">10. Sign-off and Tape-out<\/span><\/h3><p><span style=\"font-weight: 400;\">After design passes all checks (DRC\/LVS\/STA\/Power), it\u2019s ready for sign-off, meaning engineering teams, RTL, physical, verification and sign-off engineers \u2014 review data.<\/span><\/p><h5><span style=\"font-weight: 400;\">Tape-out<\/span><\/h5><p><span style=\"font-weight: 400;\">The final result, a verified GDSII\/OASIS layout, is sent to the foundry to manufacture the silicon.<\/span><\/p><p><span style=\"font-weight: 400;\">Tape-out marks the end of the design cycle and the beginning of fabrication.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Why Physical Design Matters<\/span><\/h3><p><span style=\"font-weight: 400;\">The physical design flow is where logic meets reality. It\u2019s a demanding phase where:<\/span><\/p><ul><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Abstract constructs become real silicon structures<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Electrical effects, manufacturing rules and performance targets all collide<\/span><\/li><li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Engineers use both art and tool-driven automation to achieve an optimal result<\/span><span style=\"font-weight: 400;\"><br \/><br \/><\/span><\/li><\/ul><p><span style=\"font-weight: 400;\">Failing to adequately perform physical design can result in chips that don\u2019t meet performance targets, waste area, consume too much power, or aren\u2019t manufacturable.<\/span><\/p><p>\u00a0<\/p><h3><span style=\"font-weight: 400;\">Final Thoughts<\/span><\/h3><p><span style=\"font-weight: 400;\">Understanding what happens after RTL is a <\/span><i><span style=\"font-weight: 400;\">must<\/span><\/i><span style=\"font-weight: 400;\"> for anyone pursuing a VLSI or ASIC\/FPGA design career. Today\u2019s industry demands engineers who can connect <\/span><i><span style=\"font-weight: 400;\">code to silicon<\/span><\/i><span style=\"font-weight: 400;\">, leverage automation while mastering concepts like timing, placement, routing, verification and power, not just writing RTL.<\/span><\/p><p><span style=\"font-weight: 400;\">Whether you aim to be a physical design engineer, STA expert, verification engineer, or ASIC design lead, mastering the physical design flow is foundational. This deep dive equips you to understand real chip design challenges and prepares you for advanced topics like DFT (Design for Test), PPA (Power, Performance, Area) optimization, and advanced node challenges at 7nm and beyond.<\/span><\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>In modern VLSI chip design, the journey doesn\u2019t stop at writing RTL. In fact, the RTL (Register Transfer Level) representation is just the beginning. It\u2019s a high-level functional model that describes what a design should do, not how it will be physically implemented on silicon. That transformation from abstract logic to a manufacturable silicon layout [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[8],"tags":[],"class_list":["post-9043","post","type-post","status-publish","format-standard","hentry","category-vlsi"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.7 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>What Happens After RTL? Physical Design Flow Explained | Inskill<\/title>\n<meta name=\"description\" content=\"Learn what happens after RTL in VLSI design. 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