DFT Training

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DFT Training

Course Duration : 220 hours with live lab sessions

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About Course

DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.


DFT Training will focus on all aspects of testability flow including DFT basics,  various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.


... As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.

Curriculum

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ASIC & VLSI Design Flow
Session covering complete flow overview from product requirements to Post silicon validation.
Advanced Digital Design
2 weeks dedicated course focusing on all aspects of Digital design.
www.vlsiguru.com/digital-design-complete
Verilog programming basics
3 Weeks of Verilog training covering all the aspects of Verilog required for DFT engineer
This course is done in parallel with Advanced Digital design course
Linux OS
1 week training on Linux OS and hands on
TCL Scripting
1 week training on TCL scripting for flow automation
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DFT Basics
SoC Scan architecture overview
Types of Scan
ATPG DRC Debug
ATPG Simulation Mismatch Debug
DFT Diagnosis
JTAG
MemoryBIST
LogicBIST
Scan and ATPG
Test compression technigues
Hierarchical Scan Design
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Full SOC flow - DFT
DFT Architecture and Basics
Test Plan
Different DFT schemes
Comparison between Functional and DFT Vectors
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Understanding of SCAN Insertion
Scan methodology
Types of Scan
Top-down and Bottom-up Approach
Scan insertion Flow
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Scan insertion Scripts
Multiple Clock domains
Design Rule Checking
Pre-DRC and Post DRC
Lock up and Terminal lockup latches
Hands-on Scan insertion
Assignments
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Introduction to compression
Compression Architecture
Decompressor and Compactor
Compression Ratio
DRC Analysis
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Modular Compression
X-Masking logic
Hands-on Compression
Assignments
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Scan insertion with compression
On-chip clocking for at-speed testing
Hierarchical Scan Design
Bypass mode
Hands on Scan and compression
Interaction session scan and compression
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Memory faults
Algorithms
Diagnostic mode
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Memory faults
Algorithms
Diagnostic mode
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MBIST Hands on project
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ATPG Overview
Different types of Faults
Types of fault models
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ATPG Overview
Different types of Faults
Types of fault models
ATPG algorithm
Understand complete Test procedure
Hands on Project
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DRC analysis
Test Coverage and Fault Coverage
Coverage improvement Analysis
Chain and Capture patterns
Assignments
Simulations- No-timing and Timing simulations
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At speed fault model (In detail)
Understanding Transition fault ATPG
Two pulse generator
Test procedure
Launch on capture and Launch on Shift
Top-off Pattern generation
Path delay
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Introduction to JTAG
JTAG State Machine
Boundary Scan
Different instructions
Industry Standard Project
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Introduction to LBIST
SPYGLASS
Revision
Mock Interview

Course videos

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Unit 1 Digital Basic 00:07:05
Unit 2 Dft basics & tools 01:28:37
Unit 3 Idea of scan, modes of scan & controllability obeservability 00:36:56
Unit 4 Answers for Digital Questions 01:05:12
Unit 5 scan styles 00:16:17
Unit 6 scanchain and disadvantages of scan 00:26:09
Unit 7 flow of scan insertion with in DRC violations 01:18:42
Unit 8 linux commands 00:24:08
Unit 9 continution of DRC violations 02:12:28
Unit 10 Top down and bottom up approaches and scan inputs & outputs 00:26:27
Unit 11 scan chain balencing & clock mixing and edge mixing 01:52:34
Unit 12 scan chain reordering 00:16:01
Unit 13 diff between scan and nonscan 00:15:24
Unit 14 lab ses on scan 01:32:24
Unit 15 scan topics revision 00:04:43
Unit 16 lab ses explaining about linux commands ,testproc file & netlist 01:31:52
Unit 17 Edt & its architecture 00:33:01
Unit 18 compression ratio 00:32:06
Unit 19 revision of previous topics & lab 00:24:39
Unit 20 Edt bypass & masking concepts 01:02:58
Unit 21 Edt pins 00:19:37
Unit 22 Edt compressor 00:25:09
Unit 23 whole Edt concepts explaining with ppt 00:41:03
Unit 24 whole Edt concepts explaining with ppt 00:31:14
Unit 25 Atpg basics & stuck at faults 00:52:56
Unit 26 fault models p2 & fault categeries & Dalgorithem 01:24:39
Unit 27 ATPG flow & some Questons 00:50:30
Unit 28 revision of scan,EDT & ATPG 00:31:26
Unit 29 lab ses on scan 00:17:11
Unit 30 Edt lab ses & explained about generated edt output files 01:04:43
Unit 31 diff b/w Edt & scan testprocfiles and Edt &bypass testprocfiles in lab 01:01:31
Unit 32 Edt lab ses & explained about generated edt output files 01:08:12
Unit 33 ATPG coverage formulas & introduction about fault classes 00:22:23
Unit 34 Discussion on doubts 00:12:14
Unit 35 ATPG fault classes >>> untestable faults 01:20:43
Unit 36 ATPG Testable Faults 00:57:37
Unit 37 coverage Analysis 00:50:51
Unit 38 revision of all fault classes 03:03:23
Unit 39 Factors effecting the coverage 02:48:21
Unit 40 revision & Transition Delay Fault & diff b/w Transition &stuck_at 01:01:08
Unit 41 Pathdelay FaultModel 00:24:57
Unit 42 IDDQ fault model 00:32:13
Unit 43 revision of all previous concepts DFT,scan by using ppt 01:53:51
Unit 44 Architecture of EDT & DRC Rules 00:55:28
Unit 45 EDT lab ses 01:49:06
Unit 46 complete edt concept explained by presenting ppt 01:18:30
Unit 47 ATPG fault classes & IDDQ fault model & ATPG flow 00:41:38
Unit 48 lab ses on ATPG Dofile 00:50:29
Unit 49 Lab ses on ATPG 02:26:33
Unit 50 simulations basics and Timing&Notiming Simulations 00:52:00
Unit 51 ATPG lab revision & simulation lab & checking for outputfiles 00:43:38
Unit 52 Question & ANSWERS on all DFT,SCAN,ATPG,SIMULATIONS 01:02:40
Unit 53 Notiming & timing Simulations 00:19:05
Unit 54 lab on simulation 00:19:05
Unit 55 Lab ses on Simulations & how to identify simulation mismatches 02:26:33
Unit 56 revison & reasons for simulation mismatches 00:55:00
Unit 57 features of occ 02:00:04
Unit 58 Atpg iddq 01:04:25
Unit 59 Introduction to JTAG & JTAG module sample block 00:46:45
Unit 60 Boundary scan 01:00:52
Unit 61 JTAG TAP controller 01:24:40
Unit 62 Memory introduction & architecture 00:53:20
Unit 63 memory faults 00:41:51
Unit 64 memory faults & memory algorithms 01:38:10
Unit 65 Ram architecture 00:19:20
Unit 66 Mbist tools & Mbist capabilities & Mbist algorithms & flow of mbist in mentor 00:50:18
Unit 67 Mbist faults & mbist implementation 00:46:13
Unit 68 Mbist lab 01:25:06
Unit 69 Mbist lab 03:03:55
Unit 70 lab on memory simulaton 01:20:12
Unit 71 lab on TSDB directory 01:12:28
Unit 72 wrapper insertion 01:19:25
Unit 73 lab on mbist synthesis 01:07:00
Unit 74 lab on mbist flow step3 on scan_insertion 00:45:32
Unit 75 wrapper insertion 01:33:40
Unit 76 Mbist insertion lab 00:35:50
Unit 77 ATPG lab & Gray box 01:12:24
Unit 78 topics on lab3 steps insert_mbist,insert edt_occ,synthesis,scan_insertion 01:21:11
Unit 79 lab on mbist 00:30:45
Unit 80 Hierarchical scan 01:18:02
Unit 81 labs on mbist atpg,mbist patterns on netlist 02:33:26
Unit 82 lab on mbist on coreb 01:54:30
Unit 83 ppt on steps for mbist ..>hierarchical scan for coreb 00:46:45
Unit 84 how to handle 00:30:28
Unit 85 lab on pll handling in mbist 01:54:45


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