+
| Introduction |
| Protocol overview |
| I2C architecture |
| Signal Descriptions |
| I2C transactions |
| Write |
| Read |
| Multiple Masters, Multiple slaves |
+
| UVC architecture |
| UVC components |
| UVC types |
| Master, Slave |
| Active, Passive |
| UVC test scenario listing down |
| UVC component coding |
| Driver, Sequencer, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
Course videos
+
| Unit 1 | I2C Protocol, I2C Controller Verilog Coding | 01:36:39 | |
| Unit 2 | I2C Controller Verilog coding and TB | 01:18:50 | |
| Unit 3 | I2C Protocol revision | 00:04:45 | |
| Unit 4 | I2C Controller UVM TB | 01:03:07 |
Benefits of eLearning:
- - Access to the Instructor - Ask questions to the Instructor who taught the course
- - Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready