About Course
Verilog for Design & Verification (VG-VERILOG) is a 46 hours of theory and 30 hours of labs course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate.
Student may also opt for course on advanced digital design and basic analog design conceptsAdvanced Digital Design Training.
Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG
Verilog language constructs with detailed examples on each construct usage
Multiple Design Coding & Testbench development
Access to Questasim tool
Hands on labs & Hands on projects
Demo Videos
VIDEO
VIDEO
Course Videos
Unit 1
GVIM for Verilog coding skills.
02:28:21
Unit 2
Implementing combinational logic using Verilog
02:15:03
Unit 3
Implementing combinational logic using Verilog
02:07:41
Unit 4
Introduction to Verilog language constructs
02:04:14
Unit 5
Vector, Integer, and Real data types
00:39:54
Unit 6
Clock generation"
01:22:16
Unit 7
Arrays, $Display, $Moniter
00:54:48
Unit 8
SEED
00:05:59
Unit 9
String
00:12:43
Unit 10
Hierarchical modeling
00:59:25
Unit 11
Parameter
00:19:56
Unit 12
Memory
01:31:50
Unit 13
Memory back door access
01:25:30
Unit 14
Task and function
0:44:13
Unit 15
Automatic Task Functions
00:14:24
Unit 16
Operators
00:44:20
Unit 17
Operators - Part2
00:50:46
Unit 18
Hierarchical modeling
00:23:56
Unit 19
Port connections
00:09:11
Unit 20
Statement process
00:27:24
Unit 21
Abstraction levels
01:12:42
Unit 22
Blocking non blocking
00:54:57
Unit 23
Synthesis examples
00:04:56
Unit 24
Procedural statements
00:45:21
Unit 25
Prime number generation
00:19:28
Unit 26
Pipelining
00:34:14
Unit 27
Shift register CDC
00:14:32
Unit 28
Intra and Inter delay statements
00:12:18
Unit 29
System task and system functions
00:36:02
Unit 30
Compiler directives
00:16:14
Unit 31
XMR
00:02:22
Unit 32
Signal Strength
00:05:28
Unit 33
Primitives
00:05:28
Unit 34
VPI and PLI
00:04:56
Unit 35
revision
00:03:21
Unit 36
Scheduling delay questions
00:12:01
Unit 37
Verilog good programming style
00:14:22
Unit 38
FSM
01:06:53
Unit 39
Pattern detector
00:40:02
Unit 40
APB
00:36:55
Unit 41
Synchronous FIFO"
00:54:00
Unit 42
Synchronous FIFO - Part2"
01:07:43
Unit 43
Asynchronous FIFO
00:07:18
Unit 44
Asynchronous FIFO Part2
01:24:22
Unit 45
Asynchronous FIFO Part3
00:33:45
Unit 46
Interrupt Controller
01:17:36
Unit 47
Interrupt Controller Part-2
01:59:12
Unit 48
PISO
01:29:07
Unit 49
PISO part-2
01:32:29
Unit 50
SPI Controller
01:40:23
Unit 51
SPI Controller part-2
01:09:17
Unit 52
Dual Port RAM
00:04:29
Unit 53
CRC calculation
00:28:20
Unit 54
CRC
00:29:17
Unit 55
I2C Protocol and Controller
00:57:29
Curriculum
1 : Verilog Language Constructs
How Verilog differs from other programming languages?
Verilog language concepts
Registers, nets
Vectors, Array
Memories
Data types
Operators
Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
Procedural Blocks
Continuous assignments
Procedural Statements
Generate
State Machines
Gate Level Implementation
Hierarchical modeling
Verilog Programming Interface(& PLI)
Pipelining
FSM : Mealy and Moore
FSM State encoding styles
2 : Verilog hands on design and verification projects
Flipflop (Synchronous & Asynch Reset), Latch
Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
Shift register implementation
Half adder, full adder, multiplexer
Dual port memory write, read design & testbench
encoder, decoder, various gates
Primitive implementation using table, endtable
Pattern detector
Coin counter for tea vending machine
Traffic light controller(TLC)
CRC generation code
Watchdog timer implementation
Synchronous FIFO
Asynchronous FIFO
Memory implementation
example to showcase race condition using blocking assignments
system task usage: $display, $monitor, $strobe
PLI, VPI implementation
Memory controller RTL understanding, architecture understanding
Clock generation with Duty cycle & Jitter
Interrupt Controller
SPI Controller
I2C Controller
UART Controller
Benefits of eLearning?
Access to the Instructor - Ask questions to the Instructor who taught the course
Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
SRINIVAS REDDY
Founder, VLSIGuru Institute
Dual Degree(VLSI Design), IIT Madras
14 years of industry experience