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| Introduction to on-chip protocols |
| Protocol overview |
| AXI revisions |
| AXI based system architecture |
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| Global signals |
| Write address channel signals |
| Write data channel signals |
| Write response channel signals |
| Read address channel signals |
| Read data channel signals |
| Low power interface signals |
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| Basic write and read transactions |
| Relationship between channels |
| Transaction structure |
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| Transaction types and attributes |
| AXI3 memory attribute signalling |
| AXI4 changes to memory attribute signalling |
| Memory types |
| Mismatched memory attributes |
| Transaction buffering |
| Access permissions |
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| AXI transaction identifiers |
| Transaction ID |
| Transaction ordering |
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| Definition of ordering model |
| Master ordering |
| Interconnect ordering |
| Slave ordering |
| Response before final destination |
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| Single-copy atomicity size |
| Exclusive accesses |
| Locked accesses |
| Atomic access signaling |
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| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
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| Low power interface signals |
| Low power clock control |
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| Interoperability principles |
| Major Interface categories |
| Default signal values |
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| VIP architecture |
| VIP components |
| VIP types |
| Master, Slave |
| Active, Passive |
| VIP test scenario listing down |
| VIP component coding |
| Driver, Generator, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
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| Enhance AXI3 VIP for AXI4 additional features |
| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
| Low power interface |
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| Introduction |
| About the protocol |
| AHB revisions |
| Operation |
| Signal Descriptions |
| Global signals |
| Master signals |
| Slave signals |
| Decoder signals |
| Multiplexor signals |
| Transfers |
| Basic transfers |
| Transfer types |
| Locked transfers |
| Transfer size |
| Burst operation |
| Waited transfers |
| Protection control |
| Memory types |
| Secure transfers |
| Bus Interconnection |
| Interconnect |
| Address decoding |
| Read data and response multiplexor |
| Slave Response Signaling |
| Slave transfer responses |
| Data Buses |
| Data buses |
| Endianness |
| Data bus width |
| Clock and Reset |
| Clock and reset requirements |
| Exclusive Transfers |
| Introduction |
| Exclusive Access Monitor |
| Exclusive access signaling |
| Exclusive Transfer restrictions |
| Atomicity |
| Single-copy atomicity size |
| Multi-copy atomicity |
| User Signaling |
| User signal description |
| User signal interconnect recommendations |
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| UVC architecture |
| UVC components |
| UVC types |
| Master, Slave |
| Active, Passive |
| UVC test scenario listing down |
| UVC component coding |
| Driver, Sequencer, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
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| APB protocol introduction |
| Signal descriptions |
| Transfers |
| Operating states |
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| Develop APB UVC for master and slave |
| APB master UVC validation using slave UVC |
Course videos
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| Lecture 1(APB SES1) | "Protocol basics, Protocols background, How to differentiate protocols, Types of Protocols(APB,AXI,AHP), How do we choose among various protocols? with Analogy, Steps to follow for learning any protocol, APB Detailed Explanation, signals, How transaction happens in APB, APB Timing diagram, APB Signal description." | 38:34 | |
| Lecture 2(APB SES2) | "SOC Design Architecture Explanation, APB Timing diagram Explanation, State diagram explanation, APB UVC Development, Developing all components top module, interface, design, test library, apb_environment, apb_slave, apb_agent, apb_sequencer, apb sequence, apb_driver, apb_monitor, apb_coverage" | 45:25 | |
| Lecture 3(AXI SES1) | "Protocol basics, Protocols background, How to differentiate protocols, Types of Protocols(APB,AXI,AHP), Performance, AXI Channels, Concept of ID, AXI Multiple transaction in concurrent with Home loan Analogy, AXI signals, AXI write phases, AXI read phases, Out of order, Overlapped tx, Overlapped tx, AWBURST(FIXED,INCR,WRAP), Aligned& Unaligned transfer, WRAP& INCR Calculations, Practical application of Wrapping, Little endian, Big endian, Features of AXI, AXI timing diagrams Analysing." | 3:31:12 | |
| Lecture 4(AXI SES2) | Multiple Processors in signal processor system, Cache coherency, ACE(AXI Coherency Extension, AXI VIP template coding, AXI VIP functionality coding, AXI transaction coding(Adding fields, methods, constraints), AXI Generator coding, Scenario Generation, Implementing FIXED, INCR, WRAP tests, Developing a basic slave model, Implementing hand shaking signals (REQ, ACK). | 4:07:12 | |
| Lecture 5(AXI SES3) | Program block, Why BFM is required?, Developing complete AXI slave coding, complete axi_bfm coding, Developing AXI monitor, Interface. Developing AXI coverage, AXI Assertions. | 1:50:06 | |
| Lecture 6(AXI SES4) | Implementing AXI complex scenarios (Overlapping txs, Out of order txs, Interleaved txs, Locked transfers, exclusive transfrs, Protected transfers), Steps for implementing all these scenarios & Implementing the scenarios in AXI VIP. | 0:25:21 | |
| Lecture 7(AXI SES5) | Developing AXI UVC from VIP, Implementing all uvm components by using existing code, Implementing function new, creating phases, registering to factory to existing code, Developing AXI Transaction, top file, AXI Interface, AXI Slave bfm, AXI Driver, AXI Sequencer, AXI configuration file, AXI Sequence library, Test library, AXI agent, AXI monitor, AXI coverage. | 1:08:07 | |
| Lecture 8(AHB SES1) | Protocol Basics, ARM Processor types, Detailed Explanation of AHB Protocol, Role of Arbiter, Arbitration Phase, AHB Example, AHB Signals& their decoding, Handshaking Signals Overview, Priority Arbitration, Round Robin Arbitration, Arbitration Phase All Signals, Address Phase, Data Phase, Basic Transfer Explanation with the clk edge, Wait state, Analysing the timing diagram& its Importance for Verification Engineer, Pipelining Detailed Explanation, Signal Phases, AHB Transaction Example, Little endian architecture, Big endian architecture, Hprot, Hresp(OKAY,ERROR,RETRY,SPLIT), Htrans Possibilities, AHB features, Aligned& Unaligned transfer, transfer, Burst Transfers , Differences between incrementing and wrapping transfers, Wrapping Detailed Explanation& Calculations. | 3:35:08 | |
| Lecture 9(AHB SES2) | AHB Architecture, Hprot signal Explanation with Analogy, Bufferable, Cacheable, L1, L2 Cache, Incrementing& Wrapping Calculations, Two cycle response, HRESP, HRESP signal responses(Okay, Error, Retry, Split), AHB arbitration, Exclusive transfers, AHB UVC, What is UVC?, Why is it required? How to develop UVC? What type of UVC to use?, UVC Development, Template UVC Development, Functionality Development, ahb_drv coding, AHB UVC functional coding(Coding fields, required methods & constraints). | 03:43:15 | |
| Lecture 10(AHB SES3) | Early burst termination, AHB UVC Functional Coding, ahb_tx coding(fields, methods, constraints), resp, exokay are non rand, why?, Implementing wrap test, How to get rid of unknown 'x' values in waveform after simulation, Driver coding(drive_tx, arb_phase, addr_phase, data_phase), responder, monitor, coverage, UVM Preparation focus areas, Finding the issues with AHB UVC. | 3:51:01 | |
| Lecture 11(AHB SES4) | Fixing the Debug issues in AHB UVC, Developing more tests( Checking different burst types, Checking different port, Checking exclusive access, checking write/reads), Setting UVC parameters in ahb_uvc_config file, Resolving new issues, Implementing test with multiple write/reads, Implementing final AHB UVC without any debugging issues. | 4:10:16 |
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