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Numbering system |

Signed number |

Unsinged number |

1’s complement |

2’s complement |

Karnaugh maps |

Truth table |

Excitation table |

Timing diagrams |

Address bus |

Data bus |

Control signals |

Handshake signals |

Pipelining |

Flipflop |

Setup time |

Hold time |

FF Using NAND |

FF using NOR |

FF using J-K latch |

FF using latch |

How to calculate setup time, hold time |

SR FF to JK FF conversion |

DFF to TFF conversion |

JK FF to DFF |

Latch |

Difference between latch & Flipflop |

Various types of FF’s, Latch’s |

Counters (with practical applications) |

Gray counter |

Ring counter |

Johnson counter |

In a 3 bit Johnson counter, 2 states are unused, what are they |

Modulo-n counter |

Ripple counter |

FIFO |

Synchronous FIFO |

Asynchronous FIFO |

Practical applications of FIFO |

Difference between RAM & FIFO |

What is FIFO? How to Calculate the Depth of FIFO? |

Data transfer synchronization between components |

FIFO |

Handshake |

Race condition |

Show a design example with race condition |

How to fix race condition |

What is race around condition, how to fix it? |

Meta stability |

Multiplexer |

Use MUX to create AND, OR, NAND, NOR, XOR, XNOR |

Use MUX to create FF, Latch |

XOR to buffer |

XOR to Inverter conversion |

NAND to inverter |

Design 4 input NAND gate using 2 input NAND gates |

Design all gates using 2:1 MUX |

input NAND gate using min no of 2 input NAND Gates |

input NOR gate using min no of 2 input NOR Gates |

input XNOR gate using min no of 2 input XNOR Gates |

How to implement a Master Slave flip flop using a 2 to 1 Mux? |

Design D Latch using 2:1 mux |

Design D Latch from SR Latch |

Decoder, encoder, priority decoder |

Parity generation |

Practical uses of parity generation |

Half adder, full adder |

FA using HA |

Truth table for HA, FA, Mux, counters |

Buffer, inverter |

Practical uses |

PLL, VCO, clock generation |

PLL LMN parameters |

Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies |

Clock domain crossing |

What are the different ways synchronize between two clock domains? |

Synchronizers : 2 stage, 3 stage |

T-FF |

Reset |

Practical uses, how reset distribution works |

Synchronous reset, Asynchronous reset |

Power management in SOC |

VD, PD, CD |

State machines |

Gray code encoding |

One-hot encoding |

Binary encoding |

Moore state machine |

Mealy state machine |

Difference between Moore and Mealy state machines |

Register |

Using FF |

Memories |

SDRAM |

SRAM |

NAND FLASH |

NOR FLASH |

How they function |

How they are modeled |

Synthesis |

Given RTL code, draw the synthesis diagram |

Predict design output |

Given a design with various gates and FF, draw the timing diagram |

Predict the output |

Gate level simulation |

What is x-prop |

Different causes of x-prop |

SDF format |

Different types of delays in digital circuits |

Propagation delay |

Rise delay, fall delay |

Transmission delay |

How to fix setup time violation |

How to fix hold time violation |

What is multi cycle path |

What is false path, impact on circuit operation |

Why multi stage synchronizers are masked for x-prop checks |

Clock distribution |

Draw a logic to distribute clock for minimal clock latencies in various blocks of SOC |

How to minimize clock jitter |

How to reduce clock latency |

How clock gating works |

How to achieve 180 degrees phase shift |

Clock skew? How to reduce clock skew? |

What is glitch? What causes it (explain with waveform)? How to overcome it? |

Active low and active high |

Why interrupts are active low |

PISO, SIPO |

How do we achieve multiply and division using register shift |

How to achieve multiple by 3 using shift? |

Comparator |

Write gate logic to compare 2 8-bit signals |

Difference between full substractor and half substractor |

Implement full substractor from full adder |

Digital design interview questions |

The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotation. |

You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is “ripple” (cascading), Which circuit has a less propagation delay? Why? |

Design a circuit for finding the 9’s complement of a BCD number using 4-bit binary adder and some external logic gates? |

Design a circuit that calculates square of a number |

CRC calculation logic |

Logic diagram |

Pattern detector FSM |

Give the circuit to extend the falling edge of the input by 2 clock pulses? |

Circuit design for various requirements |

### Course videos

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Unit 1 | Agenda | 00:02:35 | |

Unit 2 | why learn digital design | 00:17:15 | |

Unit 3 | Number system and radix format and Hex to Binary mapping | 02:01:24 | |

Unit 4 | Number of bits required and compliments | 02:42:12 | |

Unit 5 | logic_gates and Realization of gates using universal gates | 02:16:50 | |

Unit 6 | Assignment question discussion on mux using cmos, homework questions | 01:06:22 | |

Unit 7 | Rules for NAND and NOR and problems | 00:21:14 | |

Unit 8 | kmap | 00:05:45 | |

Unit 9 | Boolean expression simplification | 00:53:02 | |

Unit 10 | SOP and POS representation, minterm and maxterm representation | 01:16:59 | |

Unit 11 | argument on SOP and POS | 00:22:22 | |

Unit 12 | Assignment question discussion on logic gates,SOP and POS | 00:27:20 | |

Unit 13 | revision on sop and pos, sigma and pi | 00:01:01 | |

Unit 14 | Combinational_circuits-multiplexer | 01:08:45 | |

Unit 15 | Combinational_circuits- De-mux | 00:05:10 | |

Unit 16 | Combinational_circuits- Encoder | 00:08:32 | |

Unit 17 | Combinational_circuits- Priority Encoder | 00:16:19 | |

Unit 18 | Combinational_circuits- decoder | 00:12:58 | |

Unit 19 | Combinational_circuits - Comparator | 00:13:12 | |

Unit 20 | Combinational_circuits - Half adder and full adder | 00:14:55 | |

Unit 21 | Combinational_circuits - Half_sub and full_sub | 00:12:29 | |

Unit 22 | examples on combinational circuits | 00:07:14 | |

Unit 23 | C | 02:03:51 | |

Unit 24 | BCD | 00:46:34 | |

Unit 25 | gray code | 00:30:20 | |

Unit 26 | Assignment questions discussion | 00:12:32 | |

Unit 27 | Assignment questions discussion | 03:52:35 | |

Unit 28 | Assignment questions discussion | 01:42:06 | |

Unit 29 | Introduction to sequential logic, why clk is required, Basic concept of storage | 01:09:36 | |

Unit 30 | Latch, various tables in digital electronics, sr latch | 00:27:19 | |

Unit 31 | Assignment question discussion | 01:40:35 | |

Unit 32 | JK Latch , T LATCH, D Latch | 00:57:01 | |

Unit 33 | Excitation table of flip-flop, characteristics equation | 00:05:16 | |

Unit 34 | Flip flop latch | 00:08:15 | |

Unit 35 | implementaing ff behaviour ,latch using mux, implementaing ff using latch | 00:24:33 | |

Unit 36 | JK ff implementaing uing jk latch, Dff using mux | 00:27:51 | |

Unit 37 | Transmission gate d ff | 00:24:46 | |

Unit 38 | flip flop realization using other flip flop | 00:43:34 | |

Unit 39 | Dff Setup time and hold time, Different types of digital circuit analysis, Max frequency of | 00:18:00 | |

Unit 40 | Synchronous reset and Asynchronous reset Dff, Preset and clear | 00:10:47 | |

Unit 41 | circuit based on ff- counters | 01:00:04 | |

Unit 42 | Introduction of frequency division , asyn counters part1 | 01:10:55 | |

Unit 43 | Introduction of frequency division , asyn counters part2 | 01:38:54 | |

Unit 44 | clock_frequency_division | 03:27:18 | |

Unit 45 | Assignment question discussion | 04:00:05 | |

Unit 46 | frequency division and multiplication Doubt discussion, flip flop doubt discussion, and assignment question SES13 22JUNE2021 SR | 00:29:00 | |

Unit 47 | freq division doubt discussion | 00:38:14 | |

Unit 48 | edge detector circuits | 00:19:49 | |

Unit 49 | Shift registers | 00:23:08 | |

Unit 50 | Synchronizers | 00:24:35 | |

Unit 51 | pipelining | 01:38:02 | |

Unit 52 | FSM-Mealy and moore problems,doubt discussion | 01:41:51 |

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