Physical Design Training with hands on ICC2 projects

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Physical Design Training

Course Duration : 17 weeks

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About Course

Physical Design Training is a 4 months course (+1.5 months for freshers covering Device fundamentals, IC fabrication, timing concepts. advanced digital design, analog design basics, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow(DC, ICC II, Star RC, PT, ICV). It is among widely used PnR flow in industry.


Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (Block level and Full chip level) from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.


... Physical Design Training is supported using 15+ assignments covering all aspects physical design implementation flow including practical aspects. Assignments are detailed and well structured to cover all the aspects of Physical Design. These assignments will solved as part of course lectures. Student will have 12 months access to tool from date of course registration.
VLSIGuru Institute is setup in 2012, helped 1000+ students find right career opportunities. VLSIGuru offers affordable Physical Design Training in Bangalore and Noida. Course will Online Physical Design Training is offered for students based out of Bangalore.
Below are the Physical design Training topics.
Netlist to GDSII flow :
Initial Design Setup
Importing design

Floorplanning
Power Planning
Placement
Scan chain re-ordering and re-partitioning
Global Routing
Clock Tree Synthesis
Detailed Routing
Power Analysis (static and dynamic)
Engineering Change Order flow (ECO)
Design For Manufacturability

Curriculum

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Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
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Conductors, Semiconductors, Insulators
Intrinsic and Extrinsic Semiconductors
Diode
BJT
MOSFET (NMOS, PMOS, CMOS)
FinFET
Device Fabrication
Significance of above aspects with Physical Design flow
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Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles
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Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Setup time, Hold time, timing closure, fixing setup time and hold time violations
STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
www.vlsiguru.com/digital-design-complete
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Introduction to all the majorly used keywords on PD flow
VLSI Technology concepts
Resistance, Capacitance, Inductance
Parasitic capacitance
L-C-R circuit analysis
RC circuit significance with circuit delay
Clock distribution concepts, skew
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Introduce TCL
Why TCL?
TCL Script Processing
Understand TCL uses and strengths
Writing simple TCL scripts
TCL for VLSI scripting
TCL : Main Features
TCL in EDA
TCL shell (tclsh)
Working with TCL scripts (UNIX)
TCL Interpreter in SoC Design Tools
TCL Scripting for SoC Design
TCL Commands
Variables
Substitution and Command Evaluation
Operators
Mathematical Functions
Procedures
Control flow : if, if-else, switch, for, foreach, while, break and continue
string, string operations
List, List manipulation
Arrays, array methods
Working with files
Command line arguments
Regular expressions
Complete TCL Scripts
TCL Packages
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Basics of Synthesis
High Level Synthesis Flow
Reading of Verilog RTL File
Target and Link Libraries
Resolving References with Link Libraries
Reading hierarchical Designs
Reading ddc design
Analyse & Elaborate Commands
Constraining and Compiling RTL
Post Synthesis Output Data
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Constraining Register to Register Paths
Constraining Inputs Paths
Constraining Outputs Paths
Virtual Clock
Load Budgeting
Default Path Groups
Creating User-defined Path Groups
Prioritizing Path Groups
Timing Reports
Analyzing Timing Reports
Defining a Clock with additional options
Input Delay with additional options
Output Delay with additional options
Pre-CTS versus Post CTS Clock Latencies
Independent IO Latencies
Output Delay with Network Latency
Output Delay with Source Latency
Different IO versus Internal Latencies
IO Clock Latencies
Handling Different IO Vs Internal Latencies
Virtual External Clock Latencies
Included External Clock Latencies
Multiple Synchronous Clocks
Multiple Clocks Input Delay
Maximum Internal Input Delay
Multiple Clock Output Delay
Maximum Internal Output Delay
Inter Clock Uncertainty
Generated Clocks
Mutual Exclusive Synchronous Clocks
Logically Exclusive Clocks
Multiple Clocks per Register
Cross Talk Analysis
Asynchronous Clocks
Multi Cycle Paths and Constraints
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High Level Multi-Voltage Design Concepts
Supplies and Power Domains
Power Ports and Nets
Level Shifters
Power States and PS Table
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IC Compiler II Library Manager
ICC Compiler II NDM Cell Library
Cell Library Characteristics
Library Manager Flow
Tech Only NDM Library
Technology-Only Library Flow
Technology File
Read TLU+ Files
Tech Library Preparation
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Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction
Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction
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Initial Floorplanning settings
Define Pad Instances (Physical Cells)
Pad Instance co-ordinates
Start Floorplaning
Core Die Size setting
Floorplanning of Pad Instances
Pad Filler Insertion
Define Pad Ring Power Grid
Macro Instance constraints
Macro Instance Array creation
Macro Instance Orientation
Anchor based and Relative Placement of Macro Instances
Macro Instance-Channel settings
Macro Instance placement - Manual
Congestion probability around Macro Instances
Defining Placement Blockages
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Running placement
Defining placement strategies
In Place Optimization
Hierarchical Placement
Relative Placement
Congestion analysis and reduction
Macro placement changes to reduce congestion
Standard Cell Placement Constraints
Halo creation for instances
Congestion Analysis with Standard Cell placement
Local Congestion Reduction
Density Screen and Placement Blockage for Standard Cells
Congestion Aware Placement
Re-Check Macro Placement for better Congestion relief
Create Balanced Buffer Trees for High Fanout Net
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Defining Power Structure
Logical Power/Ground Connections
Setting Power Network Constraints
Create and Analyze Power Structure
Change Power Constraints and Re-Createto meet IR requirements
Power Ground Pin connection and create Power Rails
Power Network Checks for IR and Resistance
Placement Blockage for Power Network
Incremental Placement
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Re-Order Scan connectivity within Chain
Re-Partition Scan connectivity across Chains
SCANDEF file based Scan Chain Re-Ordering
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Congestion checks for Overflow again
RC extraction for Net Parasitics
Check Timing for Max Analysis
Run Timing/Congestion aware Placement
Logic Re-Structuring for Placement and Timing
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Check Pre-CTS timing based on Global Routing and Detailed Placement
Setting Clock Constraints such as Target Skew Target Insertion Delay
Clock Root Attributes as Stop, Float and Exclude Pins
Building for Generated and Gated Clocks
Don't Touch attribute on existing Clock Tree structure
Defining Clock Buffers and Inverters.
Set Clock Tree Timing DRCs.
Non-Default Clock Routing rules setting
Perform Clock Tree Synthesis and Clock Tree Optimization
Reduce Hold Violations in Data paths and Scan Paths
Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
Synchronous Clock Balancing
Cross-Clock Delay Balancing
Logical Hierarchy aware CTS
Max and Min Analysis and subsequent Optimization
Fixing Violations
CTS Optimization across other modes and PVT corners (MMMC)
Skew and Insertion Delay checks
Checking Crosstalk on Clock Network
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Pre-Route check points
Routing fundamentals
Global Route
Detail Routing
Track Assignment and Route
Refining Detailed Route
Over the Macro routing
Non-Preferred Routing direction
Clock Net Routing
Initial Data path routing
Redundant VIA insertion setting
Post Detailed Route Optimization
Fixing DRC Violations
Post Detailed Route Delay Calculation Algorithms
Crosstalk Delay and Noise Analysis and Fix
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Check Leakage Power Dissipation
VT Cell swap for power and timing trade-off
Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
Reduce Dynamic power
Meet Total Power target
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Functional ECO
Timing ECO
Metal Only ECO using Spare Cells for base frozen designs
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2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification
Projects based on multi voltage domain
Student will be working on 3rd project independently with trainer/mentor support.
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Antenna Rules and Fixes
Critical Area Analysis
Wire Spreading and widening
Setting minimum metal jog length
Filler Cell Insertion
Metal Fill
Timing Checks after Metal Fill
Parasitic Extraction for SignOff timing analysis
Export Netlist
Export GDSII
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Facing interviews effectively
Industry work culture
Group discussions

Course videos

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Lecture 1 VLSI Design flow Session1 02:52:37
Lecture 2 VLSI Design flow Session2 02:01:39
Lecture 1 Digital Session1 03:18:36
Lecture 2 Digital Session2 03:11:05
Lecture 3 Digital Session3 02:55:05
Lecture 4 Digital Session4 03:07:10
Lecture 5 Digital Session5 02:55:39
Lecture 6 Digital Session6 02:42:33
Lecture 7 Digital Session7 03:35:13
Lecture 8 Digital Session8 01:53:34
Lecture 1 Linux Session1 01:10:00
Lecture 2 Linux Session2 01:51:39
Lecture 3 Linux Session3 02:22:40
Lecture 4 Linux Session4 02:11:10
Lecture 5 Linux Session5 01:33:52
Lecture 6 Linux Session6 01:34:18
Lecture 1 PERL Session1 02:26:37
Lecture 2 PERL Session2 02:37:48
Lecture 3 PERL Session3 02:51:34
Lecture 4 PERL Session4 02:51:00
Lecture 5 PERL Session5 02:10:00
Lecture 6 PERL Session6 03:18:50
Lecture 1 Verilog Session1 03:00:13
Lecture 2 Verilog Session2 03:17:19
Lecture 3 Verilog session3 04:18:16
Lecture 1 Revision Management 02:00:00
Lecture 1 PD Basics Session1 01:31:28
Lecture 2 PD Basics Session2 02:00:01
Lecture 3 PD Basics Session3 02:06:47
Lecture 4 PD Basics Session4 02:19:34
Lecture 5 PD Basics Session5 01:44:12
Lecture 6 PD Basics Session6 02:11:25
Lecture 7 PD Basics Session7 01:52:19
Lecture 8 PD Basics Session8 01:49:11
Lecture 1 Cmos Session1 01:31:28
Lecture 2 Cmos Session2 01:40:18
Lecture 3 Cmos Session3 01:44:13
Lecture 4 Cmos Session4 02:00:06
Lecture 5 Cmos Session5 01:21:49
Lecture 6 Cmos Session6 01:41:32
Lecture 7 Cmos Session7 01:56:06
Lecture 8 Cmos Session8 02:03:28
Lecture 1 TCL Session1 02:42:02
Lecture 2 TCL Session2 01:22:32
Lecture 3 TCL Session3 01:53:50
Lecture 4 TCL Session4 02:06:00
Lecture 5 TCL Session5 43:53:00
Lecture 6 TCL Session6 00:31:00
Lecture 1 Physical Design main course session#1 02:15:48
Lecture 2 Physical Design main course session#2 02:17:35
Lecture 3 Physical Design main course session#3 02:41:27
Lecture 4 Physical Design main course session#4 01:59:13
Lecture 5 Physical Design main course session#5 02:13:37
Lecture 6 Physical Design main course session#6 02:41:42
Lecture 7 Physical Design main course session#7 02:39:59
Lecture 8 Physical Design main course session#8 02:20:58
Lecture 9 Physical Design main course session#9 02:16:10
Lecture 10 Physical Design main course session#10 02:08:21
Lecture 11 Physical Design main course session#11 02:32:32
Lecture 12 Physical Design main course session#12 02:39:37
Lecture 13 Physical Design main course session#13 03:17:37
Lecture 14 Physical Design main course session#14 03:13:49
Lecture 15 Physical Design main course session#15 03:19:38
Lecture 16 Physical Design main course session#16 03:24:49
Lecture 17 Physical Design main course session#17 02:47:32
Lecture 18 Physical Design main course session#18 03:06:16
Lecture 19 Physical Design main course session#19 02:43:14
Lecture 20 Physical Design main course session#20 02:28:53
Lecture 21 Physical Design main course session#21 02:08:43
Lecture 22 Physical Design main course session#22 02:44:28
Lecture 23 Physical Design main course session#23 01:57:28
Lecture 24 Physical Design main course session#24 02:11:08
Lecture 25 Physical Design main course session#25 03:03:17
Lecture 26 Physical Design main course session#26 02:27:46
Lecture 27 Physical Design main course session#27 2:23:52
Lecture 28 Physical Design main course session#28 02:20:38
Lecture 29 Physical Design main course session#29 02:49:41
Lecture 30 Physical Design main course session#30 03:23:12
Lecture 31 Physical Design main course session#31 04:14:53


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