Overview of Basics of Dubbing , EM, IR.(Theory : 3 hrs) |
Average Dubbing Calculation and Static Analysis.(Theory : 3 hrs) |
IP Modelling Techniques (Theory : 3hrs) |
APL Characterisation(3hrs) |
Dynamic Analysis Vectorless Single Cycle and Multi Cycle Flows (Theory 3 hrs) |
Dynamic Vectored Analysis(3 hrs) |
Redhawk Signal EM(3hrs) |
Low Debugging Design Analysis(3 hrs) |
Setup of flow(3hrs) |
Day 1: |
Overview of Debugging skills. |
Labs: Understanding of Input files of Redhawk, Setting up of Redhawk Env. |
Day 2: |
Basics of Debugging, EM, IR. |
Data Preparation Generation of Collaterals from ICC |
Understanding Volcano Design. |
IP Modelling Techniques. |
Labs: |
Analyzing of APL using utilities Aqua and ACE. |
Sanity Checks of all Inputs Colleterals. |
Day 3: |
Grid Weakness Checks, Resistance Extraction. |
Labs: |
Performing PG Resistance Analysis - effective resistance of Instances, Pin Path Resistance Checks |
Missing Vias Checks, |
Analyzing Shorts, |
Disconnected Instances, |
Connectivity Checks. |
Day 4 & 5: |
Average Debugging Calculation, |
Static Analysis Theory, |
Redhawk Static IR/EM Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Debugging Calculation in Static Analysis using Toggle rate. |
Debugging Calculation in Static Analysis using BPFS. |
Doing experiments with BPFS. |
Exploration of Redhawk TCL Commands for advanced Debugging of IR Drop. |
Creation of Custom lib’s for Missing PG Arcs. |
Exploration of Redhawk Explorer. |
Exploration of Debugging Maps. |
Package and PAD Constraints. |
Results Exploration and Debugging. |
Debugging EM Violations. |
Analyzing Hot spots. |
Analysis Battery Currents and Demands Currents. |
Day 6 & 7. |
Dynamic Vectorless Analysis |
Dynamic Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Plotting Instance current |
Min, Max, Avg DVD in Timing Window and min DVD in Whole Simulation Cycle. |
Analysis of Switches and its equivalent reports |
Wire IR Drops |
Exploration of DVD Histograms. |
Plotting Instance Voltage Waveform. |
Plotting Switching Histograms. |
Analyzing Switching events |
Decap Density Maps |
Dynamic Voltage Drop Movie. |
Analysis Dynamic Reports |
Design Weakness Checks |
Pad Current Checks |
Decap Efficiency Checks |
Simultaneous Switching Checks |
Frequency Domain based Demand Current Checks |
Voltage Domain based Demand Current Checks |
Cross Probing Violations in Redhawk GUI |
Hotspot Analysis Summary |
DVD Check – Instance Level Debug |
Short Path Tracing of Instances |
Debugging EM Checks |
Day 8: |
Multicycle Vectorless Analysis |
Labs: |
Correlation between Single Cycle and Multicycle analysis |
Cycle based Switching |
All labs on Dynamic Vectorless will be applicable to Multicycle |
Running Debugging IR/EM on Volcano or ORCA_TOP |
Running Redhawk on Debugging IR/EM Ansys Design. |
Assignments |
Labs: |
Static EM/IR Analysis.(6hrs) |
Dynamic EM/IR Vectorless Analysis Single Cycle.(6hrs) |
Dynamic EM/IR Vectorless Analysis Multi Cycle.(6 hrs) | Dynamic Vectored Analysis Worst Debugging Cycle.(6hrs) |
Dynamic Vectored Analysis Worst dpdt Cycle.(6 hrs) |
Signal EM Analysis.(3hrs) |
Low Debugging Design Analysis(6 hrs) |
Unit Number | Topic | Duration (Mins) |
1 | Debug techniques course overview | 5 |
2 | Memory controller debug for port level connection issue | 49 |
3 | AXI2OCP bridge debug for transaction hanging | 46 |
4 | Ethernet MAC register write read testcase debug | 120 |
5 | Register access testcase coding and debug : Front door and back door access with all 4 combinations | 155 |
6 | MAC FD transmit test coding and debug | 149 |
7 | MAC FD Transmit test debug | 155 |
8 | MAC FD receive test case coding and debug | 112 |
9 | MAC FD receive test case debug | 138 |
10 | SOC : Testcase debug techniques | 31 |
11 | SOC : Testcase debug points, verification closure | 46 |
12 | GLS - X-Prop, X Prop tracing | 11 |
13 | GLS - Memory controller timing GLS debug | 105 |
14 | GLS - Memory controller design X Prop tracing | 122 |
15 | GLS - Memory controller Unit delay simulations bringup | 125 |
16 | How to view Signals in side object in the waveform | 10 |
Overview of Basics of Dubbing , EM, IR.(Theory : 3 hrs) |
Average Dubbing Calculation and Static Analysis.(Theory : 3 hrs) |
IP Modelling Techniques (Theory : 3hrs) |
APL Characterisation(3hrs) |
Dynamic Analysis Vectorless Single Cycle and Multi Cycle Flows (Theory 3 hrs) |
Dynamic Vectored Analysis(3 hrs) |
Redhawk Signal EM(3hrs) |
Low Dubbing Design Analysis(3 hrs) |
Setup of flow(3hrs) |
Day 1: |
Overview of Dubbing skills. |
Labs: Understanding of Input files of Redhawk, Setting up of Redhawk Env. |
Day 2: |
Basics of Dubbing, EM, IR. |
Data Preparation Generation of Collaterals from ICC |
Understanding Volcano Design. |
IP Modelling Techniques. |
Labs: |
Analyzing of APL using utilities Aqua and ACE. |
Sanity Checks of all Inputs Colleterals. |
Day 3: |
Grid Weakness Checks, Resistance Extraction. |
Labs: |
Performing PG Resistance Analysis - effective resistance of Instances, Pin Path Resistance Checks |
Missing Vias Checks, |
Analyzing Shorts, |
Disconnected Instances, |
Connectivity Checks. |
Day 4 & 5: |
Average Dubbing Calculation, |
Static Analysis Theory, |
Redhawk Static IR/EM Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Dubbing Calculation in Static Analysis using Toggle rate. |
Dubbing Calculation in Static Analysis using BPFS. |
Doing experiments with BPFS. |
Exploration of Redhawk TCL Commands for advanced Debugging of IR Drop. |
Creation of Custom lib’s for Missing PG Arcs. |
Exploration of Redhawk Explorer. |
Exploration of Dubbing Maps. |
Package and PAD Constraints. |
Results Exploration and Debugging. |
Debugging EM Violations. |
Analyzing Hot spots. |
Analysis Battery Currents and Demands Currents. |
Day 6 & 7. |
Dynamic Vectorless Analysis |
Dynamic Flow |
Labs: |
Setting Up of GSR for Static Run. |
Creation of Command run file. |
Plotting Instance current |
Min, Max, Avg DVD in Timing Window and min DVD in Whole Simulation Cycle. |
Analysis of Switches and its equivalent reports |
Wire IR Drops |
Exploration of DVD Histograms. |
Plotting Instance Voltage Waveform. |
Plotting Switching Histograms. |
Analyzing Switching events |
Decap Density Maps |
Dynamic Voltage Drop Movie. |
Analysis Dynamic Reports |
Design Weakness Checks |
Pad Current Checks |
Decap Efficiency Checks |
Simultaneous Switching Checks |
Frequency Domain based Demand Current Checks |
Voltage Domain based Demand Current Checks |
Cross Probing Violations in Redhawk GUI |
Hotspot Analysis Summary |
DVD Check – Instance Level Debug |
Short Path Tracing of Instances |
Dubbing EM Checks |
Day 8: |
Multicycle Vectorless Analysis |
Labs: |
Correlation between Single Cycle and Multicycle analysis |
Cycle based Switching |
All labs on Dynamic Vectorless will be applicable to Multicycle |
Running Dubbing IR/EM on Volcano or ORCA_TOP |
Running Redhawk on Dubbing IR/EM Ansys Design. |
Assignments |
Labs: |
Static EM/IR Analysis.(6hrs) |
Dynamic EM/IR Vectorless Analysis Single Cycle.(6hrs) |
Dynamic EM/IR Vectorless Analysis Multi Cycle.(6 hrs) |
Dynamic Vectored Analysis Worst Dubbing Cycle.(6hrs) |
Dynamic Vectored Analysis Worst dpdt Cycle.(6 hrs) |
Signal EM Analysis.(3hrs) |
Low Dubbing Design Analysis(6 hrs) |
TESTIMONIALS
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I have attended the online live training from USA on Verification. The Online training along with the assignments and projects not only made me understand the concepts on Verilog, SV, UVM in depth but also helped extremely during my on-site interviews with Apple, Nvidia and Intel and I ended up getting a job at Intel as a Graphics Hardware Engineer currently working on Validation. I am glad that the VLSIGuru is providing the training on entire VLSI design flow at a very reasonable price. Highly recommended for the freshers who are looking to start their career in VLSI design in both front end or back end and for the working professionals who are looking to grow/promote to higher positions. 5 stars without a doubt ! Cheers !
I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.
The best thing about the institute is that the head of the institute teaches us one to one and make everything a cakewalk.
To be honest I didn't have any prior coding experience before
I am placed in Analog Devices Inclusive at very handsome package on Day 1 placements .
Thanks for the support.
Best Institute for VLSI DOMAIN. The Faculty is friendly.
In videos Srinivas Sir is the best in teaching.
The Lab Session are very very Good They will clear your all the doubts.
They Conduct PPT presentations Session for students for real experience and
Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
And thanks to srinivas Reddy sir and monahar sir to solve my issue.
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