Physical Design Training with hands on ICC2 projects
Physical Design Training is a 8 months course (3 months for freshers covering Device fundamentals, IC fabrication, timing concepts.
- 184 HoursCourse Duration
- 152 SessionsRecorded & Live
- 4.6/5Learner Rating
- 5000+Enrolled Learners
Course Overview
About Course
Physical Design Training is a 8 months course (3 months for freshers covering Device fundamentals, IC fabrication, timing concepts. advanced digital design, analog design basics, and UNIX OS) structured to enable aspiring engineers get in-depth knowledge of all aspects of Physical design flow from Netlist to GDSII including Floor planning, Placement, power planning, scan chain reordering, global routing, clock tree synthesis, power analysis and ECO. Course also involves multiple hands on projects using Synopsys Implementation flow(DC, ICC II, Star RC, PT, ICV). It is among widely used PnR flow in industry.
Physical Design training program is well illustrated and supported with real-time examples from the industry. Floorplanning, Placement and Routing, Clock Tree Synthesis, Final Routing and Timing Closure forms the core of the Physical Design Training program structure. Thorough and micro level wide understanding of the concepts across all the Physical Design flow would be the key highlight of this program. Complete Theory Sessions and complementing Lab Sessions with projects (Block level and Full chip level) from Netlist to GDSII, guided well by expert trainer are offered for every candidate of this Physical Design Training program.
Physical Design Training is supported using 15+ assignments covering all aspects physical design implementation flow including practical aspects. Assignments are detailed and well structured to cover all the aspects of Physical Design. These assignments will solved as part of course lectures. Student will have 4 months access to tool from date of course registration.
VLSIGuru Institute is setup in 2012, helped 1000+ students find right career opportunities. VLSIGuru offers affordable Physical Design Training in Bangalore and Noida. Course will Online Physical Design Training is offered for students based out of Bangalore.
Below are the Physical design Training topics.
Netlist to GDSII flow :
Initial Design Setup
Importing design
Floorplanning
Power Planning
Placement
Scan chain re-ordering and re-partitioning
Global Routing
Clock Tree Synthesis
Detailed Routing
Power Analysis (static and dynamic)
Engineering Change Order flow (ECO)
Design For Manufacturability
Detailed Syllabus
23 modules- Specification
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- DFT
- Custom layout
- Post silicon validation
- Conductors, Semiconductors, Insulators
- Intrinsic and Extrinsic Semiconductors
- Diode
- BJT
- MOSFET (NMOS, PMOS, CMOS)
- FinFET
- Device Fabrication
- Significance of above aspects with Physical Design flow
- Shells
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
- Makefiles
- Digital Design basics
- combinational logic
- sequential logic, FF, latch, counters
- Memories
- Setup time, Hold time, timing closure, fixing setup time and hold time violations
- STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
- www.vlsiguru.com/digital-design-complete
- Introduction to all the majorly used keywords on PD flow
- VLSI Technology concepts
- Resistance, Capacitance, Inductance
- Parasitic capacitance
- L-C-R circuit analysis
- RC circuit significance with circuit delay
- Clock distribution concepts, skew
- Introduce TCL
- Why TCL?
- TCL Script Processing
- Understand TCL uses and strengths
- Writing simple TCL scripts
- TCL for VLSI scripting
- TCL : Main Features
- TCL in EDA
- TCL shell (tclsh)
- Working with TCL scripts (UNIX)
- TCL Interpreter in SoC Design Tools
- TCL Scripting for SoC Design
- TCL Commands
- Variables
- Substitution and Command Evaluation
- Operators
- Mathematical Functions
- Procedures
- Control flow : if, if-else, switch, for, foreach, while, break and continue
- string, string operations
- List, List manipulation
- Arrays, array methods
- Working with files
- Command line arguments
- Regular expressions
- Complete TCL Scripts
- TCL Packages
- Basics of Synthesis
- High Level Synthesis Flow
- Reading of Verilog RTL File
- Target and Link Libraries
- Resolving References with Link Libraries
- Reading hierarchical Designs
- Reading ddc design
- Analyse & Elaborate Commands
- Constraining and Compiling RTL
- Post Synthesis Output Data
- Constraining Register to Register Paths
- Constraining Inputs Paths
- Constraining Outputs Paths
- Virtual Clock
- Load Budgeting
- Default Path Groups
- Creating User-defined Path Groups
- Prioritizing Path Groups
- Timing Reports
- Analyzing Timing Reports
- Defining a Clock with additional options
- Input Delay with additional options
- Output Delay with additional options
- Pre-CTS versus Post CTS Clock Latencies
- Independent IO Latencies
- Output Delay with Network Latency
- Output Delay with Source Latency
- Different IO versus Internal Latencies
- IO Clock Latencies
- Handling Different IO Vs Internal Latencies
- Virtual External Clock Latencies
- Included External Clock Latencies
- Multiple Synchronous Clocks
- Multiple Clocks Input Delay
- Maximum Internal Input Delay
- Multiple Clock Output Delay
- Maximum Internal Output Delay
- Inter Clock Uncertainty
- Generated Clocks
- Mutual Exclusive Synchronous Clocks
- Logically Exclusive Clocks
- Multiple Clocks per Register
- Cross Talk Analysis
- Asynchronous Clocks
- Multi Cycle Paths and Constraints
- High Level Multi-Voltage Design Concepts
- Supplies and Power Domains
- Power Ports and Nets
- Level Shifters
- Power States and PS Table
- IC Compiler II Library Manager
- ICC Compiler II NDM Cell Library
- Cell Library Characteristics
- Library Manager Flow
- Tech Only NDM Library
- Technology-Only Library Flow
- Technology File
- Read TLU+ Files
- Tech Library Preparation
- Top Level, Sub-System Level and Block Level Design Setup
- Set up initial Design Implementation
- Loading Netlist from Synthesis
- Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
- Flow Setup and Design Setup
- Loop-back to Synthesis for Correlation issues correction
- Top Level, Sub-System Level and Block Level Design Setup
- Set up initial Design Implementation
- Loading Netlist from Synthesis
- Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
- Flow Setup and Design Setup
- Loop-back to Synthesis for Correlation issues correction
- Initial Floorplanning settings
- Define Pad Instances (Physical Cells)
- Pad Instance co-ordinates
- Start Floorplaning
- Core Die Size setting
- Floorplanning of Pad Instances
- Pad Filler Insertion
- Define Pad Ring Power Grid
- Macro Instance constraints
- Macro Instance Array creation
- Macro Instance Orientation
- Anchor based and Relative Placement of Macro Instances
- Macro Instance-Channel settings
- Macro Instance placement - Manual
- Congestion probability around Macro Instances
- Defining Placement Blockages
- Running placement
- Defining placement strategies
- In Place Optimization
- Hierarchical Placement
- Relative Placement
- Congestion analysis and reduction
- Macro placement changes to reduce congestion
- Standard Cell Placement Constraints
- Halo creation for instances
- Congestion Analysis with Standard Cell placement
- Local Congestion Reduction
- Density Screen and Placement Blockage for Standard Cells
- Congestion Aware Placement
- Re-Check Macro Placement for better Congestion relief
- Create Balanced Buffer Trees for High Fanout Net
- Defining Power Structure
- Logical Power/Ground Connections
- Setting Power Network Constraints
- Create and Analyze Power Structure
- Change Power Constraints and Re-Createto meet IR requirements
- Power Ground Pin connection and create Power Rails
- Power Network Checks for IR and Resistance
- Placement Blockage for Power Network
- Incremental Placement
- Re-Order Scan connectivity within Chain
- Re-Partition Scan connectivity across Chains
- SCANDEF file based Scan Chain Re-Ordering
- Congestion checks for Overflow again
- RC extraction for Net Parasitics
- Check Timing for Max Analysis
- Run Timing/Congestion aware Placement
- Logic Re-Structuring for Placement and Timing
- Check Pre-CTS timing based on Global Routing and Detailed Placement
- Setting Clock Constraints such as Target Skew Target Insertion Delay
- Clock Root Attributes as Stop, Float and Exclude Pins
- Building for Generated and Gated Clocks
- Don't Touch attribute on existing Clock Tree structure
- Defining Clock Buffers and Inverters.
- Set Clock Tree Timing DRCs.
- Non-Default Clock Routing rules setting
- Perform Clock Tree Synthesis and Clock Tree Optimization
- Reduce Hold Violations in Data paths and Scan Paths
- Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
- Synchronous Clock Balancing
- Cross-Clock Delay Balancing
- Logical Hierarchy aware CTS
- Max and Min Analysis and subsequent Optimization
- Fixing Violations
- CTS Optimization across other modes and PVT corners (MMMC)
- Skew and Insertion Delay checks
- Checking Crosstalk on Clock Network
- Pre-Route check points
- Routing fundamentals
- Global Route
- Detail Routing
- Track Assignment and Route
- Refining Detailed Route
- Over the Macro routing
- Non-Preferred Routing direction
- Clock Net Routing
- Initial Data path routing
- Redundant VIA insertion setting
- Post Detailed Route Optimization
- Fixing DRC Violations
- Post Detailed Route Delay Calculation Algorithms
- Crosstalk Delay and Noise Analysis and Fix
- Check Leakage Power Dissipation
- VT Cell swap for power and timing trade-off
- Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
- Reduce Dynamic power
- Meet Total Power target
- Functional ECO
- Timing ECO
- Metal Only ECO using Spare Cells for base frozen designs
- 2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification
- Projects based on multi voltage domain
- Student will be working on 3rd project independently with trainer/mentor support.
- Antenna Rules and Fixes
- Critical Area Analysis
- Wire Spreading and widening
- Setting minimum metal jog length
- Filler Cell Insertion
- Metal Fill
- Timing Checks after Metal Fill
- Parasitic Extraction for SignOff timing analysis
- Export Netlist
- Export GDSII
- Facing interviews effectively
- Industry work culture
- Group discussions
Session-wise Content
152 sessions · 184h 51m- 1Introduction to digital system25m
- 2Number system introduction and Radix conversion1h 1m
- 3Compliments of the number systems and 1 s and 2 s Compliments1h 33m
- 49 s and 10 s Compliments, 7 s and 8 s Compliments and 15 s and 16 s Compliments1h 5m
- 5Gates and its truth table and Why NAND is preferred over NOR gate1h 12m
- 6NAND and NOR Realization1h 7m
- 7SOP and POS form, minterm, Maxterm canonical SOP and POS form56m
- 8Boolean equations Switching equations26m
- 9Boolean minimization techniques and K -map(2-variables,3-variables,4-variables) and Logisim tool introduction1h 40m
- 10Implicants, PI, EPT, NEPT and RPI55m
- 11K -map(5-variables,6-variables)26m
- 12K -map with don t care functions27m
- 13Building of combinational logic circuits (code converters)50m
- 14Code converters continues43m
- 15Arithmetic circuits (HA, FA and Parallel Adder)1h 4m
- 16Subtractors using compliments (HS, FS)1h 2m
- 17MSI circuits (Multiplexers) and Gates using Muxs1h 7m
- 18Boolean function Implementation using Mux53m
- 19FA using Mux and Mux tree1h 2m
- 20Demultiplexers42m
- 21Decoders41m
- 22Decoders configurations and priority encoders1h 2m
- 23Comparators57m
- 24Introduction to sequential logic ckts, Basic storage element (NOR latch)1h 9m
- 25NAND latch45m
- 26Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems1h 24m
- 27Master-Slave combination and Edge triggering Flip flops1h 13m
- 28Revision of latch, Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems59m
- 29Master-Slave combination and its limitations7m
- 30Edge triggering and its advantages51m
- 31Asynchronous inputsOverriding inputs of Flip flops, Characteristic equations and Excitation table of Flip flops1h 5m
- 32Flip flop conversions18m
- 33Applications of the Flip flops (Counters - Asynchronous up and down counters)1h 8m
- 34Asynchronous Mod-N counters1h
- 35Asynchronous updown counters, Timing considerations of the flip flops and limitations of the Asynchronous counter51m
- 36Design of synchronous counters1h 27m
- 37Registers, shift registers and its configurations, universal shift registers1h 2m
- 38Counters based on shift registers (Ring and Johnson counters)51m
- 39Frequency divider circuits1h 41m
- 40Frequency multiplier and Edge detector circuits36m
- 41Introduction to FSM, Implicit and Explicit FSM1h 3m
- 42FSM sequence detector of melay and moore model1h 42m
- 43Problems on FSM1h 22m
- 44Assignment discussion34m
- 45Synchronizers to change the pipelining.25m
- 46Synchronizers to change the pipelining.1h 42m
- 47FSM-Mealy and moore problems,doubt discussion26m
- 48D Flip flop using transmission gate2h 45m
- 49ASIC FLOW SES12h 51m
- 50ASIC FLOW SES22h 28m
- 51ASIC FLOW SES32h 50m
- 52ASIC FLOW SES41h 45m
- 53UNIX SES12h 5m
- 54UNIX SES22h 20m
- 55UNIX SES32h 7m
- 56UNIX SES450m
- 57UNIX SES52h 52m
- 58UNIX SES62h 48m
- 59UNIX SES72h 36m
- 60UNIX SES81h 56m
- 61UNIX LAB SES1h 27m
- 62UNIX LAB SES2h 9m
- 63LINUX GVIM SES32m
- 64Need for Transistor?25m
- 65How MOSFET function?36m
- 66Classification of solids. What makes semiconductor special?26m
- 67Intrinsic and Extrinsic semiconductors33m
- 68PN Junction diode20m
- 69Applications of Diode52m
- 70BJT1h 2m
- 71FET basics54m
- 72MOSFET: PMOS, NMOS, CMOS1h
- 73CMOS fabrication1h 42m
- 74CMOS short channel effects12m
- 75CMOS leakage currents1h 25m
- 76FinFET20m
- 77TCL Cygwin usage basics20m
- 78TCL traning overview, Agenda40m
- 79Introduction to TCL58m
- 80How to run the TCL program50m
- 81Formal syntax of the TCL37m
- 82set, puts and gets commands1h 27m
- 83TCL Operators58m
- 84TCL Control statements1h 3m
- 85TCL Control statements (if and for statements)31m
- 86TCL Control statements (while statements)30m
- 87TCL Control statements (switch and foreach statements)24m
- 88TCL strings and its operators1h 8m
- 89Strings operators Conti...1h 4m
- 90Examples of Strings operators Conti...55m
- 91Programs on TCL Strings operators26m
- 92TCL Lists55m
- 93Programs on TCL Lists1h 1m
- 94TCL special variables30m
- 95Programs on TCL special variables35m
- 96Programs on TCL special variables Conti...54m
- 97TCL File handling operations59m
- 98Programs on TCL File handling operations56m
- 99Programs on TCL File handling operations Conti...1h 22m
- 100TCL Procedures and Programs on TCL Procedures50m
- 101TCL Procedures and Programs on TCL Procedures Conti...52m
- 102TCL Procedures and its parameters47m
- 103TCL Arrays47m
- 104TCL Associative Arrays33m
- 105Programs on TCL Arrays1h 45m
- 106TCL Dictionary48m
- 107TCL Regular expression48m
- 108Programs on TCL Regular expression46m
- 109Programs on TCL Regular expression Conti...46m
- 110Programs on TCL Regular expression Conti...1h 32m
- 111PD BASICS SES12h
- 112PD BASICS SES22h 47m
- 113PD BASICS SES32h 20m
- 114PD BASICS SES41h 45m
- 115PD BASICS SES52h 12m
- 116PD BASICS SES61h 53m
- 117PD BASICS SES71h 50m
- 118PD BASICS SES81h 10m
- 119fkf Introduction to digital system10m
- 120ASIC Design flow2h 29m
- 121Factors affecting delay and Power in CMOS2h 6m
- 122Input file - .lib file1h 46m
- 123Input file - .lef file1h 13m
- 124Input file - .tf and tlu+ file1h 15m
- 125Netlist and Hireachial design1h 30m
- 126Creating Core area and Die Area1h 32m
- 127Port Placement43m
- 128TCL Program for Port Placement using Different Commands1h 38m
- 129Macros and Type of Macros2h 1m
- 130Macro Placement Guide lines47m
- 131Blockages and Keepout Margin31m
- 132Power Reduction Techniques - Multi Voltage design37m
- 133Power Reduction Techniques - Multi Vt Cells10m
- 134Power Reduction Techniques - Clock gating Design14m
- 135UPF For Multivoltage design1h 27m
- 136Power Reduction Techniques - Power gating design1h 11m
- 137End cap cells35m
- 138TAP cells , TIE Cells DCAP and Spare cells1h 25m
- 139Power Planning1h 32m
- 140Sanity Checks at each stage and basics of timing3h 4m
- 141Setup and Hold Analysis57m
- 142In to reg and reg to out path discussion2h 21m
- 143PBA and GBA paths1h 55m
- 144Timing Exceptions1h 7m
- 145Uncertainity , Skew , transition and Driving cell1h 22m
- 146Placement goals and checks before placement stage1h 33m
- 147Inputs to placement and Placement steps2h
- 148Placement Optimization Techniques3h 9m
- 149CTS and Clock gating cells2h 3m
- 150CTS spec and Clock tree exceptions1h 38m
- 151CTS steps and CRPR2h 21m
- 152Routing2h 10m
Your Instructor
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.
The best thing about the institute is that the head of the institute teaches us one to one and make everything a cakewalk.
To be honest I didn't have any prior coding experience before
I am placed in Analog Devices Inclusive at very handsome package on Day 1 placements .
Thanks for the support.
The course at VLSI GURU very well structured and adequate for a fresher to get into VLSI domain. At VLSI GURU trained us using recorded lectures, live classes and mentor sessions ,assingments give us multiple chances to learn and doubt solving .They also provide labs and projects helped me gaining practical knowledge on the concepts .They cover every topic from basics . they conduct mock interview sessions and resume building sessions,which prepared us well for job interview
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I recently completed the Functional Verification course at VLSIGuru, and I must say it was an exceptional training experience.
The course content was comprehensive, covering all essential aspects of functional verification.
The instructors were highly knowledgeable and provided clear explanations,making complex concepts easy to understand.
The practical hands-on exercises and real-world examples greatly enhanced my learning and problem-solving skills.
The course structure was well-organized, allowing for a smooth progression from fundamentals to advanced topics.
Overall, VLSIGuru's Functional Verification course has equipped me with the necessary skills and confidence to excel in the field.
Highly recommended!
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
- Most of the times, reasoning for any institute to charge higher fee(excess of 1 lakh) is tool cost is high. It is not true.
- VLSIGuru believes in creating an educational model that is affordable and sustainable in the long run. We have been running successfully since we started training in 2012 with 3500+ students trained so far. We take pride in the fact that, it is VLSIGuru which made other institutes also to offer courses in 30K to 50K range, otherwise it used to be much higher.
- Institute owns the office facility, hence we avoid rental expense. Keeping it aside, we also find it difficult to comprehend why course fee should be in excess of 1 Lakh.
- Good understanding VLSI Technology basics(CMOS, FinFET, etc)
- Digital design concepts
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year