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Custom Layout Design Training | Optimize Your Design Skills

Custom Layout Training

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Custom Layout Training

About Course

Custom layout Basic and adavanced training is 8 months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and io layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO's and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.

Majority of graduates lack good foundation in digital and analog design concepts, make them under prepared for industry requirements. Custom layout training will enable the candidate for job opportunities within 3 months from the start of course. Complete 5 months training ensures that the candidate is an expert in the domain.

Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law's, Diode-operation, MOSFET's, MOSEFT operations, second order effects, FinFET's, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL's, ADC's, DAC's, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.

Theory Demo


Fee Structure
Curriculum

Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Refer to Advanced digital design training page for detailed course contents
www.vlsiguru.com/digital-design-complete
Linux/UNIX OS, Shell
Working with files, directories
Commonly used commands
Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor
Basic Passive and Active devices
Ohms law, Kirchoff laws
Basic of circuit understanding
MOSFET Basics, Operations, few simple circuits & second order effects.
MOSFET Detailed fabrication process.
FinFET working, Fabrication, advantages & disadvantages.
Layout Editor Tool
Understanding the schematic symbols and parameters
Creating and managing libraries and cell
Commands for Layout editing.
Commands for schematic editing.
Verification : DRC and LVS
Antenna effect, latchup, Electromigration, IR Drop
Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
Resistor, Capacitor layout techniques
CMOS and BiCMOS layout techniques
Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Mismatches & Matching.
Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects).
Noises & Coupling.
Different Types of process - Advantages & Disadvantages - Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet.
Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines.
Packaging
Std Cell & Memories.
IO Layout Guidelines : High speed IOs and High Speed Interfaces.
Sense amplifier & Bit cell development
Why memory layout different than analog layout
Memory layout flow
Types of memory layout (SRAM/DRAM/ROM)
Introduction to SRAM memory layout
Fixing few manually created leaf-cell errors which impact
Abutment issues
SRAM memory design architecture
Words line and address line
SRAM rows and column design
Building blocks of SRAM
Memory Bit cell
Row decoder
Word line driver
Sense amplifier
Control block
Misc digital logic.
Pitch Calculation for blocks.
Power Planning
High speed Analog Layout
RF Layout guidelines with Transmission lines and inductor concepts
Handling clocks
Analog Circuits & Layout guidelines
Single & Multi stage differential opamp layout
current mirror layout
PLL, DLL and Oscillators
LDO and other regulators
ADCs & DACs
Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
Large drivers.
LNA & Mixers.
input pair, differential routing, Power routing, offset minimizing
Power/Signal IR Drop
cross-talk and coupling
Electrostatic Discharge
Deep Submicron Layout Issues
Shallow Trench Isolation (LOD)
Well Proximity Effect.
Design Rule Checks
Layout Versus Schematic (LVS)
Electrical Rule Checks (ERC)
Antenna Checks
Latch-up
Reliability checks like EM and IR analysis
Design for manufacturability (DFM)checks
Electrostatic discharge (ESD) path checks
Assignments and multiple hands on projects
Best Practices & Interview Questions.

Benefits of eLearning?
  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Course Highlights

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TESTIMONIALS

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FAQ

  1. Digital and anlog design concepts

  1. Session notes
  2. Lab documents with
  3. detailed steps
  4. User guides