DFT Interview preparation
Scan Insertion, need of scan insertion, scan DRCs, clearing Scan DRCs.Scan Compression, need of scan compression, EDT architecture, deciding no.
- 51 HoursCourse Duration
- 47 SessionsRecorded & Live
- 4.6/5Learner Rating
- 400+Enrolled Learners
Course Overview
About Course
Course content
- Scan Insertion, need of scan insertion, scan DRCs, clearing Scan DRCs.
- Scan Compression, need of scan compression, EDT architecture, deciding no. of internal chains and external channels.
- Need of ATPG, fault simulation, fault classes, fault categories, fault models (SA, TDF, IDDQ, PDF), On-chip Clock Controller (OCC), different types of patterns, coverage analysis and improvement.
- Simulations, it’s need and simulation mismatch debug.
- JTAG, it’s need, TAP architecture, JTAG FSM, Boundary Scan.
- IJTAG architecture, advantage of IJTAG over JTAG
- Memory faults, algorithms, Tessent MBIST implementation and Architecture.
- Hierarchical Scan, Scan Wrappers.
Detailed Syllabus
1 modules- Interview preparation
- .vimrc
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
- Interview preparation
Session-wise Content
47 sessions · 50h 47m- 1scan insertion, scan chain operation, need of scan insertion1h 9m
- 2Benefits of scan insertion, scan methodologies, types of scan cells1h 1m
- 3Clocks propagation need of OCC, Need of slow frequency clock during shift, Clock gating, Full Scan Vs Partial Scan1h 22m
- 4DRC in scan insertion, Clock controllability DRC, Set/Reset controllability DRC1h 6m
- 5Potential Race condition, Feedback Loop DRC, Bus Contention DRC, X-Source DRC1h 4m
- 6Potential Race condition, Feedback Loop DRC, Bus Contention DRC, X-Source DRC1h 31m
- 7Domain mixing problem and its fix54m
- 8Scan insertion Flow, Practical Examples2h 29m
- 9Practical Examples1h 20m
- 10Latches, Shift Registers1h 5m
- 11Reports and Outputs of Scan Insertion1h 2m
- 12Scan Compression and its need, Dedicing no. of external channels and internal chains, Components of EDT1h 5m
- 13Decompressor40m
- 14Compressor, Masking Logic29m
- 15How patterns are loaded42m
- 16Decoders (1-hot, x masking), EDT bypass1h 3m
- 17ATPG, Fault simulation, Defect, Fault, Error, D algo, Fault coverage, Test Coverage, Questions on Fault simulation, Coverage1h 14m
- 18Questions on Fault simulation44m
- 19Advantage of connecting TE of ICG to SE, Advantage of declaring reset as a clock, Fault Aliasing42m
- 20Untestable, Testable (Detected, Posdet)49m
- 21Testable (ATPG Untestable)1h 16m
- 22Testable (Undetected)37m
- 23ATPG Flow, Practicals52m
- 24Practicals (Coverage Analysis and Improvement)1h
- 25Transition Delay Fault Model50m
- 262 ways to detect TDF (LOC, LOS)22m
- 27Why we can expect only 80-85% coverage for TDF58m
- 28Path Delay Fault Model, IDDQ Fault Model, Practicals1h 42m
- 29Fault Categories, ATPG for bypass, Possibility of getting Tracing violation1h 3m
- 30Pattern Classification42m
- 31On-chip clock controller (OCC)1h 9m
- 32Simulation1h 30m
- 33Simulation Mismatch Debug1h 5m
- 34JTAG1h 36m
- 35Boundary Scan1h 31m
- 36Memory Faults, Memory Algorithms1h 20m
- 37IJTAG Tessent MBIST implementation MBIST Architecture Grouping of Memories1h 3m
- 38MBIST insertion, Simulation Practicals1h 2m
- 39MBIST run output files explanation31m
- 40EDT OCC insertion practicals explanation, CoreA level IJTAG network explanation29m
- 41Synthesis, Scan Insertion (CoreA level) Wrappers, Graybox Generation2h 12m
- 42ATPG, Simulation, MBIST patterns on netlist (CoreA level)25m
- 43CoreB level labs,Mbist insertion,simulation,EDT OCC insertion,scan, ATPG, Simulation,Pattern re-targetting, MBIST1h 11m
- 44Advantage of IJTAG,Level 4 projects MBIST insertion, pin mux logic1h 8m
- 45Static Timing Analysis (STA) questions47m
- 46Reasons for MBIST simualation mismatch debug and fixes38m
- 47(DFT_ADV_OCT batch)advantages of IJTAG over JTAG2h 17m
Your Instructor
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
What Our Students Say
Best Platform for VLSI DOMAIN. The Faculty is friendly.
In videos Srinivas Sir is the best in teaching.
The Lab Session are very very Good They will clear your all the doubts.
They Conduct PPT presentations Session for students for real experience and
Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
And thanks to srinivas Reddy sir and monahar sir to solve my issue.
Faculties are well experienced and very helpful.
I joined the online weekend classes but all my doubts and concepts were cleared by faculty members.
They even provide extra time if needed to assist you.
The training I received here for SystemVerilog was one of the best.
It helped me out in a long run in better understanding language usage for Design Verification during my Master's program, as well as to crack most of my interviews.The small projects I worked upon here, did helped me a lot for my Masters and on the other side did improved my skills.
In a single word, I can put up like, I got my basics right!!!!:)
I was really happy with the way the Institute has structured the course to help students to figure out their own way to improvise one's skills. Thank you for all your immense support.
Keep up the good work:)
I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.
The best thing about the institute is that the head of the institute teaches us one to one and make everything a cakewalk.
To be honest I didn't have any prior coding experience before
I am placed in Analog Devices Inclusive at very handsome package on Day 1 placements .
Thanks for the support.
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides