LPDDR5(X) protocol training
WCK ClockingInitialization and TrainingLPDDR5 State DiagramMode Register DefinitionLPDDR5 OperationsCommand Constraint and AC timingAC TimingDie configuration, Package ballout, Pin Definition
- 35 HoursCourse Duration
- 94 SessionsRecorded & Live
- 4.6/5Learner Rating
- 5000+Enrolled Learners
Course Overview
About Course
- WCK Clocking
- Initialization and Training
- LPDDR5 State Diagram
- Mode Register Definition
- LPDDR5 Operations
- Command Constraint and AC timing
- AC Timing
Die configuration, Package ballout, Pin Definition
Detailed Syllabus
9 modules- Features
- Functional Description
- Pad Definition and Description Pin per byte LPDDR5/LPDDR5X Bank Architecture LPDDR5 Address Translation Table Bank architecture transition Burst Operation
- Pad Definition and Description
- Pin per byte
- LPDDR5/LPDDR5X Bank Architecture
- LPDDR5 Address Translation Table Bank architecture transition Burst Operation
- LPDDR5 Address Translation Table
- Bank architecture transition
- Burst Operation
- LPDDR5 SDRAM Addressing
- Speed Grade
- Burst Sequence
- Power-up, Initialization and Power-off Procedure
- Voltage Ramp and Device Initialization
- Dual VDD2 Rail setting (MR13 OP[7]) and its change
- Reset Initialization with Stable Power
- Power-off Sequence
- Uncontrolled Power-off Sequence
- Training
- ZQ Calibration ZQ Reset Multi-die Package Considerations ZQ External Resistor, Tolerance, and Capacitive Loading Flow Chart Examples Command Bus Training Three Physical Mode Register Command Bus Training Mode1 Command Bus Training Mode1 (FSP with DVFSQ enable) Command Bus Training Mode2 Command Bus Training Mode2 (FSP with DVFSQ enable) CA VREF Training DQ VREF Training WCK2CK Leveling Write-leveling called in LPDDR4 Duty Cycle Adjuster (DCA) Duty Cycle Adjuster Range Relationship between WCK waveform and DCA Code Change The relationship between DCA Code Change and DQ output/RDQS timing Read DCA (Duty Cycle Adjuster) Duty Cycle Monitor (DCM) READ DQ Calibration WCK-DQ Training RDQS Toggle Mode Enhanced RDQS Training Mode Read/Write-based WCK-RDQS_t Training Rx Offset Calibration Training
- ZQ Calibration
- ZQ Reset
- Multi-die Package Considerations ZQ External Resistor, Tolerance, and Capacitive Loading Flow Chart Examples
- Multi-die Package Considerations
- ZQ External Resistor, Tolerance, and Capacitive Loading
- Flow Chart Examples
- Command Bus Training
- Three Physical Mode Register Command Bus Training Mode1 Command Bus Training Mode1 (FSP with DVFSQ enable) Command Bus Training Mode2 Command Bus Training Mode2 (FSP with DVFSQ enable)
- Three Physical Mode Register
- Command Bus Training Mode1
- Command Bus Training Mode1 (FSP with DVFSQ enable)
- Command Bus Training Mode2
- Command Bus Training Mode2 (FSP with DVFSQ enable)
- CA VREF Training
- DQ VREF Training
- WCK2CK Leveling
- Write-leveling called in LPDDR4
- Write-leveling called in LPDDR4
- Duty Cycle Adjuster (DCA)
- Duty Cycle Adjuster Range Relationship between WCK waveform and DCA Code Change The relationship between DCA Code Change and DQ output/RDQS timing
- Duty Cycle Adjuster Range
- Relationship between WCK waveform and DCA Code Change
- The relationship between DCA Code Change and DQ output/RDQS timing
- Read DCA (Duty Cycle Adjuster)
- Duty Cycle Monitor (DCM)
- READ DQ Calibration
- WCK-DQ Training
- RDQS Toggle Mode
- Enhanced RDQS Training Mode
- Read/Write-based WCK-RDQS_t Training
- Rx Offset Calibration Training
- Mode Register Assignment and Definition
- Mode Register Assignment and Definition in LPDDR5
- Mode Register Assignment and Definition in LPDDR5X
- Mode Register Definition
- Truth Table
- Command Truth Table
- WCK Operation
- WCK2CK Synchronization operation
- Row Operation
- Read/Write Operation
- Refresh Operation
- Other Operation
- Reliability & Power-optimization
- Dynamic Voltage and Frequency Scaling (DVFS) Data Copy Low Power Function Write X operation Post Package Repair (PPR) Refresh Management Command Refresh Management Enhancement (ARFM) Decision Feedback Equalization (DFE) Link ECC Single-ended mode for Clock, Write Clock, and RDQS Enhanced WCK Always On Mode Pre-Emphasis for DQ output Rank to Rank AC Parameter
- Dynamic Voltage and Frequency Scaling (DVFS)
- Data Copy Low Power Function
- Write X operation
- Post Package Repair (PPR)
- Refresh Management Command
- Refresh Management Enhancement (ARFM)
- Decision Feedback Equalization (DFE)
- Link ECC
- Single-ended mode for Clock, Write Clock, and RDQS
- Enhanced WCK Always On Mode
- Pre-Emphasis for DQ output
- Rank to Rank AC Parameter
- Effective Burst Length (BL/n) Definition
- Command Timing Constraints
- Read to Write Timing (tRTW)
- Read to Write Timing (tRTW)
- Auto Precharge Command Timing Constraints
- CAS Command Timing Constraints
- Training Related Timing Constraints
- MRR/MRW Timing Constraints
- Rank to Rank Command Timing Constraints
- Core AC Timing Parameters by Speed Grade
- Mode Register Assignment and Definition in LPDDR5
- Core AC Timing Parameters for LPDDR5X
Session-wise Content
94 sessions · 18h 12m- 1LPDDR5 enhancements12m
- 1LPDDR5 elearning course overview7m
- 2LPDDR5 features overview7m
- 2LPDDR5 - New clocking scheme16m
- 3Pad definitions and description8m
- 4Bank architecture20m
- 5Addressing20m
- 5Channel addressing example (Processor -> Controller -> LPDDR5)21m
- 6Speed grades4m
- 7Burst Sequence5m
- 8Power off sequence5m
- 8Power up and initialization sequence13m
- 8WCK Clocking9m
- 9Simplified LPDDR5 State Diagram8m
- 10Mode register summary - LPDDR5, LPDDR5X17m
- 11Mode register definition (MR0, MR1)12m
- 12Mode register definition (MR3 - MR20)22m
- 13Mode register definition (MR38 - MR72)28m
- 14Command truth table13m
- 15WCK2CK synchronization22m
- 16Row operations: Activate, Precharge, Auto Precharge18m
- 17burst read operation11m
- 18burst write operation9m
- 19read write latency7m
- 20write recovery time3m
- 21masked write operation7m
- 22Refresh operation34m
- 23Refresh command timing constraints10m
- 24Optimized refresh11m
- 25Self refresh operation11m
- 26Partial array self refresh4m
- 27Power down entry command10m
- 27Power down entry and exit timing diagrams17m
- 28Deep sleep mode15m
- 29Mode register write4m
- 29Mode register read12m
- 30Frequency set point26m
- 31DDR ODT basics33m
- 32On die termination for CA bus, Data bus, and WCK_t/c33m
- 33Non-target DRAM ODT18m
- 34Asynchronous NT ODT19m
- 35NT ODT - Rank2Rank write to read timing diagram5m
- 36NT ODT setting by MRW command4m
- 37NT ODT behavior unification5m
- 38Input clock stop and frequency change8m
- 39VREF Current generator5m
- 40Thermal Offset5m
- 41Temparature sensor7m
- 42Multi purpose command3m
- 43tWCK2DQ interval oscillator.16m
- 44Interval Oscillator matching error4m
- 45WCK2DQX Oscillator Readout timing4m
- 46DVFS16m
- 47Data Copy Low power function14m
- 48Write X Operation10m
- 49Initialization and training14m
- 50Dual VDD2 rail setting6m
- 51ZQ calibration basics11m
- 52Training - ZQ calibration22m
- 53ZQ calibration - Command based calibration17m
- 54ZQ calibration - ZQ resistor sharing7m
- 55ZQ calibration - ZQ Reset3m
- 56ZQ calibration - Multi die considerations10m
- 57Command bus training mode1, Physical mode registers22m
- 58Command bus training mode1 for single and multi rank systems25m
- 59Command bus training mode2 sequence10m
- 60Command bus training mode 2 sequence for single and multi rank systems16m
- 61WCK2CK Leveling11m
- 62Duty Cycle Adjuster10m
- 63Read Duty Cycle Adjuster4m
- 64Duty Cycle monitor8m
- 65Read DQ Calibration13m
- 66WCK DQ Training12m
- 67WCK DQ Training7m
- 68RDQS Toggle mode10m
- 69Read Write based WCK RDQS T-training5m
- 70Rx Offset Calibration training2m
- 71Post Package Repair10m
- 72Enhancements20m
- 73Refresh management command12m
- 74Refresh management threshold13m
- 75Refresh management enhancement5m
- 76Decision feedback Equalization12m
- 77Link ECC6m
- 78Link ECC Check matrix22m
- 79Single ended mode for clock writeclock and rdqs12m
- 80Enhanced WCK always on mode5m
- 81Pre-emphasis for DQ output2m
- 82Rank to rank AC parameter and common contraint timing8m
- 83Read to Write timing Command constraint3m
- 84Auto Precharge command timing constraints4m
- 85CAS command timing constraints14m
- 86Training related timing constraints7m
- 87Rank to rank command timing constraints5m
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Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
Course does not have any pre-requisites. However any exposure to Digital design, VLSI design flow is an added advantage.
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts