USB2.0 Protocol and USB2.0 Core verification Training
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USB2.0 Protocol and USB2.0 Core verification Training
- Course Duration: 49 Hours
- 4.6 Star (Rating)
- 1500+ (Student Enrolled till Now)
About Course
Course involves 2 aspects: Training on USB2.0 protocol.
USB2.0 Core functional verification using SV & UVM
Design Architecture overview
Feature listing down
Verification plan & Test plan development
Test bench Architecture
Test bench component coding
Test case coding & debug
Coverage analysis
Course also involves 4 assignments covering USB protocol and USB core verification.
| Unit number | Topic | Duration(mins) |
| 1 | DV course labs guidance | 40:10 |
| 2 | USB2.0 protocol overview, how protocol has evolved | 01:43:30 |
| 3 | USB2.0 protocol overview, device detection, speed negotiation and device descriptors | 45:43 |
| 4 | Line states, Data transfers, Frame, microframe, USB topology, Frame format | 01:07:42 |
| 5 | USB core understanding, EP overview, core architecture, Endpoint types | 01:04:11 |
| 6 | USB core interfaces, DMA transfers, USB packet formats, Packet fields, Special packets | 58:55 |
| 7 | Isochronous, control, interrupt and bulk transfers, | 01:39:34 |
| 8 | High speed transactions - Isochronous, Bulk and interrupt transfers, USB specification reading | 01:21:02 |
| 9 | Buffer pointers, USB registers overview, USB core operation | 54:29 |
| 10 | USB DMA operation, USB transfers | 38:48 |
| 11 | revision, buffer pointers (repeat of topics) - Weekend session | 01:18:00 |
| 12 | revision, USB operation (repeat of topics) - weekend | 56:34 |
| 13 | USB test plan development - weekend | 01:20:27 |
| 14 | USB test bench development | 42:30 |
| 15 | WB and UTMI agent component coding, DUT instantiation | 01:07:57 |
| 16 | Register reset, write read testcase coding and debug | 01:48:28 |
| 17 | Register model development and integration | 01:16:18 |
| 18 | USB register testcase debug, UTMI driver coding | 01:18:46 |
| 19 | USB speed negotiation, USB Reset sequence | 01:32:01 |
| 20 | USB frame definition, USB enumeration sequence | 50:26 |
| 21 | USB configuration sequence and Interrupt handling sequence coding | 01:18:26 |
| 22 | Updating UTMI driver to drive USB frame | 54:14 |
| 23 | Debuggng the UTMI driver code for USB packet driving to the USB core | 51:13 |
| 24 | USB packet CRC error debug, Control transfer implementation | 57:14 |
| 25 | USB enumeration implementation, moving USB frame level communication to packet level communication | 01:33:25 |
| 26 | Implementing sqr-driver communication at packet level, RTL debug for test case failure | 01:27:18 |
| 27 | Setup transfer - Data phase debug | 01:31:16 |
| 28 | Isochronous transfer sequence coding and test case implementation | 01:21:19 |
| 29 | Isochronous transfer test case debug | 01:16:01 |
| 30 | Isochronous OUT transfer test case debug | 01:45:01 |
| 31 | USB bulk out and bulk in test coding and debug | 01:15:43 |
| 32 | USB bulk in test case coding and debug | 01:42:52 |
| 33 | Developing one common sequence for all testcases | 01:48:38 |
| 34 | Wishbone and SRAM interface component coding | 01:27:25 |
| 35 | UTMI monitor coding for transmit and receive interfaces | 01:11:57 |
| 36 | USB Scoreboard coding | 01:48:06 |
| 37 | Setting up regression and test case failure analysis | 01:21:10 |
| 38 | UTMI monitor update and USB scoreboard update | 01:22:47 |
| 39 | Scoreboard update for USB packet comparison | 01:41:33 |
| 40 | USB ASSIGNMENT | 01:09:31 |
Fee Structure
Curriculum
| Course involves 2 aspects: |
| Training on USB2.0 protocol. |
| USB2.0 Core functional verification using SV & UVM |
| Design Architecture overview |
| Feature listing down |
| Verification plan & Test plan development |
| Test bench Architecture |
| Test bench component coding |
| Test case coding & debug |
| Coverage analysis |
| Course also involves 4 assignments covering USB protocol and USB core verification. |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Course Highlights
- 1-1 mentor support
- Mentor guidance support for assignments
- Multiple mock interviews
- Dedicated live support sessions over weekends
TESTIMONIALS
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I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.
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They Conduct PPT presentations Session for students for real experience and
Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
And thanks to srinivas Reddy sir and monahar sir to solve my issue.
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Best place to start your career in vlsi domain.
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FAQ
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides