USB2.0 Protocol and USB2.0 Core verification Training

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USB2.0 Protocol and USB2.0 Core verification Training

About Course

Course involves 2 aspects: Training on USB2.0 protocol.
USB2.0 Core functional verification using SV & UVM
Design Architecture overview
Feature listing down
Verification plan & Test plan development
Test bench Architecture
Test bench component coding
Test case coding & debug
Coverage analysis
Course also involves 4 assignments covering USB protocol and USB core verification.

Unit Number	Topic	Duration (Mins)
1	USB2.0 protocol overview, how protocol has evolved	104
2	USB2.0 protocol overview, device detection, speed negotiation and device descriptors	46
3	Line states, Data transfers, Frame, microframe, USB topology, Frame format	68
4	USB core understanding, EP overview, core architecture, Endpoint types	65
5	USB core interfaces, DMA transfers, USB packet formats, Packet fields, Special packets	59
6	Isochronous, control, interrupt and bulk transfers,	100
7	High speed transactions - Isochronous, Bulk and interrupt transfers, USB specification reading	81
8	Buffer pointers, USB registers overview, USB core operation	55
9	USB DMA operation, USB transfers	39
10	Revision, buffer pointers (repeat of topics) - Weekend session	78
11	Revision, USB operation (repeat of topics) - weekend	57
12	USB test plan development - weekend	81
13	USB test bench development	43
14	WB and UTMI agent component coding, DUT instantiation	68
15	Register reset, write read testcase coding and debug	109
16	Register model development and integration	76
17	USB register testcase debug, UTMI driver coding	79
18	USB speed negotiation, USB Reset sequence	92
19	USB frame definition, USB enumeration sequence	51
20	USB configuration sequence and Interrupt handling sequence coding	78
21	Updating UTMI driver to drive USB frame	55
22	Debuggng the UTMI driver code for USB packet driving to the USB core	51
23	USB packet CRC error debug, Control transfer implementation	57
24	USB enumeration implementation, moving USB frame level communication to packet level communication	94
25	Implementing sqr-driver communication at packet level, RTL debug for test case failure	87
26	Setup transfer - Data phase debug	92
27	Isochronous transfer sequence coding and test case implementation	82
28	Isochronous transfer test case debug	76
29	Isochronous OUT transfer test case debug	105
30	USB bulk out and bulk in test coding and debug	76
31	USB bulk in test case coding and debug	103
32	Developing one common sequence for all testcases	109
33	Wishbone and SRAM interface component coding	88
34	UTMI monitor coding for transmit and receive interfaces	72
35	USB Scoreboard coding	108
36	Setting up regression and test case failure analysis	81
37	UTMI monitor update and USB scoreboard update	83
38	Scoreboard update for USB packet comparison	102

Curriculum

Course Content

Course involves 2 aspects:

Training on USB2.0 protocol.

USB2.0 Core functional verification using SV & UVM

Design Architecture overview

Feature listing down

Verification plan & Test plan development

Test bench Architecture

Test bench component coding

Test case coding & debug

Coverage analysis

Course also involves 4 assignments covering USB protocol and USB core verification.

Benefits of eLearning?

Access to the Instructor - Ask questions to the Instructor who taught the course
Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

Course Instructor

Dedicated Trainer Accessible On Phone / Email / Whatsapp
Trainer Exp: 15 Years

Price - ₹9,000 + GST

₹10,000 (10% Off)

10 hours left to avail at this price

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Course Highlights

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TESTIMONIALS

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Best Institute for VLSI DOMAIN. The Faculty is friendly.
In videos Srinivas Sir is the best in teaching.
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Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
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