DMA Controller Functional Verification
DMA controller is an important aspect of every SOC, which is used for peripheral to peripheral, peripheral to memory and memory to memory data transfers with minimal intervention from Processor.
- 36 HoursCourse Duration
- 13 SessionsRecorded & Live
- 4.6/5Learner Rating
- 3000+Enrolled Learners
Course Overview
About Course
DMA controller is an important aspect of every SOC, which is used for peripheral to peripheral, peripheral to memory and memory to memory data transfers with minimal intervention from Processor. Current DMA controller design has 2 cores with 8 channels per core.
DMA controller functional verification using SV & UVM, covers all the aspects of verification starting from reading the specifications, feature list down, testbench development, testbench component coding, register model development, testcase coding and regression setup, debug for coverage analysis. Course gives indepth overview of sequence development, debugging of complete testcases, etc. Course also introduces to functional and code coverage analysis.
Detailed Syllabus
4 modules- Feature list down
- Testplan development
- Functional coverage point list down
- Register list down
- Testbench architecture definition
- TB component coding
- Register model coding
- TB component integration
- Testcase development
- Register access tests: reset and wr-rd testcases
- Functional testcase coding
- Test case debug
- Regression setup using PERL script
- Regression and coverage report generation
- Functional and code coverage analysis
- Updating tests for coverage closure
- Adding new tests for coverage closure
Session-wise Content
13 sessions · 35h 31m- 1DMA CNTRL SES12h 13m
- 2DMA CNTRL SES22h 47m
- 3DMA CNTRL SES31h 27m
- 4DMA CNTRL SES42h 42m
- 5DMA CNTRL SES52h 45m
- 6DMA CNTRL SES63h 24m
- 7DMA CNTRL SES71h 30m
- 8DMA CNTRL SES82h 36m
- 9DMA CNTRL SES93h 18m
- 10DMA CNTRL SES103h 6m
- 11DMA CNTRL SES113h 26m
- 12DMA CNTRL SES123h 12m
- 13DMA CNTRL SES133h 5m
Your Instructor
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What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Good understanding of SV and UVM
- Exposure to Testbench component coding using SystemVerilog and UVM
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts