AXI Protocol and VIP Development Training
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AXI Protocol and VIP Development Training
- Course Duration: 23 Hours
- 4.6 Star (Rating)
- 800+ (Student Enrolled till Now)
About Course
AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.
AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.
Demo Videos
| Unit Number | Topic | Duration (Mins) |
| 1 | AXI Protocol introduction | 206 |
| 2 | AXI Protocol features | 109 |
| 3 | AXI Protocol advanced features | 103 |
| 4 | AXI Protocol advanced features | 65 |
| 5 | VIP development concepts, VIP template coding | 45 |
| 6 | VIP BFM and Generator coding, Testcase development | 97 |
| 7 | VIP monitor and coverage coding, Coverage report analysis | 161 |
| 8 | Reference model and checker coding, | 161 |
| 9 | Assertions coding, Advanced feature implementation | 83 |
| 10 | AXI advanced feature implementation, Slave implementation as a slave VIP | 60 |
| 11 | Advanced feature checking | 25 |
| 12 | AXI UVC Development | 68 |
| 13 | AXI Scoreboard coding - 2 different styles | 183 |
| 14 | AXI Scoreboard integration steps | 6 |
| 15 | AXI, AHB interview questions | 4 |
| 16 | AXI Interconnect development concepts | 6 |
| 17 | AXI WRAP FIXED Burst Implementation concepts | 52 |
Curriculum
| Introduction to on-chip protocols |
| Protocol overview |
| AXI revisions |
| AXI based system architecture |
| Global signals |
| Write address channel signals |
| Write data channel signals |
| Write response channel signals |
| Read address channel signals |
| Read data channel signals |
| Low power interface signals |
| Basic write and read transactions |
| Relationship between channels |
| Transaction structure |
| Transaction types and attributes |
| AXI3 memory attribute signalling |
| AXI4 changes to memory attribute signalling |
| Memory types |
| Mismatched memory attributes |
| Transaction buffering |
| Access permissions |
| AXI transaction identifiers |
| Transaction ID |
| Transaction ordering |
| Definition of ordering model |
| Master ordering |
| Interconnect ordering |
| Slave ordering |
| Response before final destination |
| Single-copy atomicity size |
| Exclusive accesses |
| Locked accesses |
| Atomic access signaling |
| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
| Low power interface signals |
| Low power clock control |
| Interoperability principles |
| Major Interface categories |
| Default signal values |
| VIP architecture |
| VIP components |
| VIP types |
| Master, Slave |
| Active, Passive |
| VIP test scenario listing down |
| VIP component coding |
| Driver, Generator, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
| Enhance AXI3 VIP for AXI4 additional features |
| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
| Low power interface |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Course Highlights
- Mentor Support for doubt clarifications
- Product company focused questions
- 49 hours of lectures
TESTIMONIALS
What Our Students Says About Inskill
I have taken training at VLSIGURU for Design and Verification course through online.
They have very experienced faculty with industrial knowledge.
The trainers explained every concept from the very basic to core concepts with good explanation.
Every doubt has been clarified with patience and in detail.
Every session os recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provided online access as well.
VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts.
Interview preparation sessions has also been conducted along with mock interviews and training sessions.
It is the best institute to gain knowledge in core domain with affordable prices.
I Thank VLSIGURU for helping me to gain knowledge in the core domain.
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I have attended the online live training from USA on Verification. The Online training along with the assignments and projects not only made me understand the concepts on Verilog, SV, UVM in depth but also helped extremely during my on-site interviews with Apple, Nvidia and Intel and I ended up getting a job at Intel as a Graphics Hardware Engineer currently working on Validation. I am glad that the VLSIGuru is providing the training on entire VLSI design flow at a very reasonable price. Highly recommended for the freshers who are looking to start their career in VLSI design in both front end or back end and for the working professionals who are looking to grow/promote to higher positions. 5 stars without a doubt ! Cheers !
Best place to start your career in vlsi domain.
They act as bridge to help students to get industry requirements for the job.
Interms of teaching they are excellent for what we paid and get less fees compared to other institutions.
Even after course completion also they support if u had any doubts.
FAQ
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to any bus protocols like I2C, SPI, etc
- Exposure to digital design concepts
Yes. Participant will gain exposure to following aspects
- VIP development for AXI3 protocol
- UVC development for AHB2 protocol
- UVC development for APB protocol
- Analysing AXI, AHB and APB timing diagrams in simulations
- Functional coverage analysis
- Assertion coding and debugging
- Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts