AXI Protocol and VIP Development Training

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AXI Protocol and VIP Development Training

About Course

AMBA Protocol training is structured to enable engineers gain perfection in AXI, AHB & APB protocols. Majority of designs are based on ARM architecture. All ARM architectures are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have detailed understanding of these protocols. SoC design debug and testbench component coding in most cases involves either AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.


AMBA Protocol training course focuses on teaching protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB2.0 and APB. Course also focus on teaching protocol testbench development concepts. Student has flexibility to choose specific protocol as well.

Demo Videos
Unit NumberTopicDuration (Mins)
1AXI Protocol introduction206
2AXI Protocol features109
3AXI Protocol advanced features103
4AXI Protocol advanced features65
5VIP development concepts, VIP template coding45
6VIP BFM and Generator coding, Testcase development97
7VIP monitor and coverage coding, Coverage report analysis161
8Reference model and checker coding,161
9Assertions coding, Advanced feature implementation83
10AXI advanced feature implementation, Slave implementation as a slave VIP60
11Advanced feature checking25
12AXI UVC Development68
13AXI Scoreboard coding - 2 different styles183
14AXI Scoreboard integration steps6
15AXI, AHB interview questions4
16AXI Interconnect development concepts6
17AXI WRAP FIXED Burst Implementation concepts52
Curriculum

Introduction to on-chip protocols
Protocol overview
AXI revisions
AXI based system architecture
Global signals
Write address channel signals
Write data channel signals
Write response channel signals
Read address channel signals
Read data channel signals
Low power interface signals
Basic write and read transactions
Relationship between channels
Transaction structure
Transaction types and attributes
AXI3 memory attribute signalling
AXI4 changes to memory attribute signalling
Memory types
Mismatched memory attributes
Transaction buffering
Access permissions
AXI transaction identifiers
Transaction ID
Transaction ordering
Definition of ordering model
Master ordering
Interconnect ordering
Slave ordering
Response before final destination
Single-copy atomicity size
Exclusive accesses
Locked accesses
Atomic access signaling
QoS signaling
Multiple region signaling
User-defined signaling
Low power interface signals
Low power clock control
Interoperability principles
Major Interface categories
Default signal values
VIP architecture
VIP components
VIP types
Master, Slave
Active, Passive
VIP test scenario listing down
VIP component coding
Driver, Generator, Monitor, Coverage, Environment
Interface, transaction, Slave model, assertions
Testbench integration
Testcase coding
Simulations and waveform analysis
Functional coverage analysis
Assertion coding and analysis
Enhance AXI3 VIP for AXI4 additional features
QoS signaling
Multiple region signaling
User-defined signaling
Low power interface

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹4500 + GST

₹5000    (10% Off)

10 hours left to avail at this price

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