Protocol Training
UART Protocol and UVC Development Training
UART Protocol training is focused on learning all the aspects of UART including architecture, signals, transactions, features, etc.
- 10 HoursCourse Duration
- 3 SessionsRecorded & Live
- 4.6/5Learner Rating
- 200+Enrolled Learners
Course Overview
About Course
UART Protocol training is focused on learning all the aspects of UART including architecture, signals, transactions, features, etc. UART UVC development is focused on developing UART master UVC and UART slave UVC. UART master and slave UVC are validated by connecting each other. This also involves developing scoreboard and checking for checking test case passing.
Detailed Syllabus
2 modules- Introduction
- Protocol overview
- UART architecture
- Signal Descriptions
- UART transactions
- Write
- Read
- UVC architecture
- UVC components
- UVC types
- Master, Slave
- Active, Passive
- UVC test scenario listing down
- UVC component coding
- Driver, Sequencer, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
Session-wise Content
3 sessions · 4h 24m- 1UART VERILOG DESIGN VERIFICATION2h 6m
- 2UART UVM_Test bench development1h 24m
- 3UART Scoreboard and checker development54m
Your Instructor
S
Sreenivas Reddy
Founder, VLSIGuru
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready