UVM essentials elearning course (VG-UVMESS) is a 38 hours course offered by Sreenivasa Reddy, Founder, VLSIGuru. Course is targeted for freshers with Systemverilog expertise. Course is structured to enable engineers develop expertise in full breadth of UVM. UVM course is targeted towards engineers looking to explore functional verification techniques involving advanced methodology concepts like factory, databases and register layer. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.

UVM elearning course is divided in to 2 aspects, initial lectures focused on in depth understanding of language constructs using detailed examples, later part of lectures focused on AHB and APB protocols, UVC development for these protocols. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc.

UVM constructs are learnt using more than 100+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc. AHB Interconnect design is used as a reference example to learn all above aspects of UVM. These examples cover more than 90% of questions asked in VLSI interviews.