FPGA Design and Verification Training

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FPGA Design and Verification Training

About Course

FPGA course is a 6 months course provides in depth exposure to complete FPGA system design flow starting from RTL coding, prototyping and validation.


FPGA Architecture
FPGA internals and I/0
FPGA timing closure
FPGA implementation by RTL mode as well as IP Mode
FPGA debugging
Software development kit environment
Booting FPGA in petalinux/ubuntu

Demo Videos
Unit NumberTopicDuration (Mins)
1FPGA DEMO SES160
2FPGA SES2152
3FPGA SES3150
4FPGA SES4152
5FPGA SES552
6FPGA SES6135
7FPGA SES765
8FPGA SES866
9FPGA SES9126
10FPGA SES1083
11FPGA SES1196
12FPGA SES12132
13FPGA SES1394
14FPGA SES1467
15FPGA SES1568
16FPGA SES1660
17FPGA SES17152
18FPGA SES18139
19FPGA SES1952
20FPGA SES2045
21FPGA SES2168
22FPGA SES2222
23FPGA SES23120
24FPGA SES24176
25FPGA SES2564
Curriculum

Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Refer to Advanced digital design training page for detailed course contents
www.vlsiguru.com/digital-design-complete
Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles
SOC Architecture overview
SOC design concepts
SOC verification concepts
SOC Components
SOC use cases
SOC Testbench architecture
SOC Test Case coding
SOC verification differences with module verification
Verilog language constructs
Verilog design coding examples covering more than 20 standard designs
www.vlsiguru.com/verilog-training/
PAL, CPLD and FPGA basics
FPGA Design Flow
Internals of FPGA and CPLD
Logic implementation
FPGA Architectures of various FPGA vendors
Anti-fuse and SRAMS
Logic elements and Look-up Tables
Dedicated multipliers
Distributed RAM
Shift registers
MMCM
Kintex
Zynq
Virtex Architectures
Introduction and usage of IP cores·
Modelsim/Icarus Verilog simulation
Design Synthesis
Design constraining and pin locking
Timing analysis
slack calculation
Data loss due to large skew
Maximum skew calculations with examples
Period constraints
Area and Power Constraints
Static Timing Analysis
FPGA programming
Translate
Map
Floor plan
Place and Route
Post map and Post P&R simulation
XDC constraints
Reading and analysing reports-post synthesis
Post map simulation
Post P·&R simulation
Configuring FPGAs
FSM Extraction
Timing Simulation using Modelsim/Icarusverilog
Programming using JTAG
Debugging techniques
Debugging using chip scope and Logic analyzers
Protocols on FPGA
High Speed SERDES
Identification of the issues/resolving
FPGA SDK environment
FPGA Device selection
PERL Interpreter
Variables
File management
Subroutines
Regular expressions
Object oriented PERL
PERL modules
Facing interviews effectively
industry work culture
Group discussions
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹45,000 + GST

₹50,000    (10% Off)

10 hours left to avail at this price

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