Digital Design Training
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Digital Design Training
- Course Duration: 44 Hours
- 4.6 Star (Rating)
- 200+ (Student Enrolled till Now)
About Course
Numbering system
Karnaugh maps
Timing diagrams
Pipelining
Flipflop
Latch
Various types of FF’s, Latch’s
Various Counters (with practical applications)
FIFO
Data transfer synchronisation between components
Race condition
Meta stability
Multiplexer, Using MUX to create various gates, FF
Decoder, encoder, priority decoder
Parity generation
Half adder, full adder
Truth table for HA, FA, Mux, counters
Buffer, inverter
PLL, VCO, clock generation
Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies
Clock domain crossing
Reset
Power management in SOC
State machines
Register
Memories
Synthesis
Predict design output
Gate level simulations
Debugging incorrect designs
Clock distribution
Active low and active high
PISO, SIPO
Comparator
Designing circuits for various requirements
CRC calculation logic
Pattern detector FSM
Interview focused questions
Give the circuit to extend the falling edge of the input by 2 clock pulses?
What are different ways multiply & Divide?
Target Audience:
BTech & MTech freshers looking for career opportunities in VLSI and InSkill domains
Experienced engineers looking to enhance Digital Design advanced concepts
FAQ:
How this course helps?
Majority of VLSI, InSkill fresher interviews focus on digital design concepts
All the VLSI Designs are driven by Digital and analog design concepts. Good fundamentals helps with quick design understanding.
What if few sessions missed?
Course is organised once every 3 months. Student can repeat with no additional fee
Demo Videos
Unit Number Topic Duration(mins) 1 Introduction to digital system 25 2 Number system introduction and Radix conversion 61 3 Compliments of the number systems and 1 s and 2 s Compliments 93 4 9 s and 10 s Compliments, 7 s and 8 s Compliments and 15 s and 16 s Compliments 65 5 Gates and its truth table and Why NAND is preferred over NOR gate 72 6 NAND and NOR Realization 67 7 SOP and POS form, minterm, Maxterm canonical SOP and POS form 56 8 Boolean equations Switching equations 100 9 Boolean minimization techniques and K -map(2-variables,3-variables,4-variables) and Logisim tool introduction 55 10 Implicants, PI, EPT, NEPT and RPI 26 11 K -map(5-variables,6-variables) 27 12 K -map with don t care functions 50 13 Building of combinational logic circuits (code converters) 43 14 Code converters continues 64 15 Arithmetic circuits (HA, FA and Parallel Adder) 62 16 Subtractors using compliments (HS, FS) 67 17 MSI circuits (Multiplexers) and Gates using Muxs 54 18 Boolean function Implementation using Mux 60 19 FA using Mux and Mux tree 62 20 Demultiplexers 41 21 Decoders 40 22 Decoders configurations and priority encoders 72 23 Comparators 57 24 Introduction to sequential logic ckts, Basic storage element (NOR latch) 69 25 NAND latch 45 26 Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems 84 27 Master-Slave combination and Edge triggering Flip flops 79 28 Revision of latch, Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems 59 29 Master-Slave combination and its limitations 7 30 Edge triggering and its advantages 51 31 Asynchronous inputsOverriding inputs of Flip flops, Characteristic equations and Excitation table of Flip flops 65 32 Flip flop conversions 18 33 Applications of the Flip flops (Counters - Asynchronous up and down counters) 68 34 Asynchronous Mod-N counters 60 35 Asynchronous updown counters, Timing considerations of the flip flops and limitations of the Asynchronous counter 51 36 Design of synchronous counters 87 37 Registers, shift registers and its configurations, universal shift registers 62 38 Counters based on shift registers (Ring and Johnson counters) 51 39 Frequency divider circuits 100 40 Frequency multiplier and Edge detector circuits 36 41 Introduction to FSM, Implicit and Explicit FSM 62 42 FSM sequence detector of melay and moore model 102 43 Problems on FSM 82 44 Assignment discussion 34 45 Synchronizers to change the pipelining. 25 46 Synchronizers to change the pipelining. 98 47 FSM-Mealy and moore problems,doubt discussion 102 48 D Flip flop using transmission gate 26
Curriculum
| Numbering system |
| Signed number |
| Unsinged number |
| 1’s complement |
| 2’s complement |
| Karnaugh maps |
| Truth table |
| Excitation table |
| Timing diagrams |
| Address bus |
| Data bus |
| Control signals |
| Handshake signals |
| Pipelining |
| Flipflop |
| Setup time |
| Hold time |
| FF Using NAND |
| FF using NOR |
| FF using J-K latch |
| FF using latch |
| How to calculate setup time, hold time |
| SR FF to JK FF conversion |
| DFF to TFF conversion |
| JK FF to DFF |
| Latch |
| Difference between latch & Flipflop |
| Various types of FF’s, Latch’s |
| Counters (with practical applications) |
| Gray counter |
| Ring counter |
| Johnson counter |
| In a 3 bit Johnson counter, 2 states are unused, what are they |
| Modulo-n counter |
| Ripple counter |
| FIFO |
| Synchronous FIFO |
| Asynchronous FIFO |
| Practical applications of FIFO |
| Difference between RAM & FIFO |
| What is FIFO? How to Calculate the Depth of FIFO? |
| Data transfer synchronization between components |
| FIFO |
| Handshake |
| Race condition |
| Show a design example with race condition |
| How to fix race condition |
| What is race around condition, how to fix it? |
| Meta stability |
| Multiplexer |
| Use MUX to create AND, OR, NAND, NOR, XOR, XNOR |
| Use MUX to create FF, Latch |
| XOR to buffer |
| XOR to Inverter conversion |
| NAND to inverter |
| Design 4 input NAND gate using 2 input NAND gates |
| Design all gates using 2:1 MUX |
| input NAND gate using min no of 2 input NAND Gates |
| input NOR gate using min no of 2 input NOR Gates |
| input XNOR gate using min no of 2 input XNOR Gates |
| How to implement a Master Slave flip flop using a 2 to 1 Mux? |
| Design D Latch using 2:1 mux |
| Design D Latch from SR Latch |
| Decoder, encoder, priority decoder |
| Parity generation |
| Practical uses of parity generation |
| Half adder, full adder |
| FA using HA |
| Truth table for HA, FA, Mux, counters |
| Buffer, inverter |
| Practical uses |
| PLL, VCO, clock generation |
| PLL LMN parameters |
| Generating X2, X3, X4, X1/2, X1/3, X1/4 clock frequencies |
| Clock domain crossing |
| What are the different ways synchronize between two clock domains? |
| Synchronizers : 2 stage, 3 stage |
| T-FF |
| Reset |
| Practical uses, how reset distribution works |
| Synchronous reset, Asynchronous reset |
| Power management in SOC |
| VD, PD, CD |
| State machines |
| Gray code encoding |
| One-hot encoding |
| Binary encoding |
| Moore state machine |
| Mealy state machine |
| Difference between Moore and Mealy state machines |
| Register |
| Using FF |
| Memories |
| SDRAM |
| SRAM |
| NAND FLASH |
| NOR FLASH |
| How they function |
| How they are modeled |
| Synthesis |
| Given RTL code, draw the synthesis diagram |
| Predict design output |
| Given a design with various gates and FF, draw the timing diagram |
| Predict the output |
| Gate level simulation |
| What is x-prop |
| Different causes of x-prop |
| SDF format |
| Different types of delays in digital circuits |
| Propagation delay |
| Rise delay, fall delay |
| Transmission delay |
| How to fix setup time violation |
| How to fix hold time violation |
| What is multi cycle path |
| What is false path, impact on circuit operation |
| Why multi stage synchronizers are masked for x-prop checks |
| Clock distribution |
| Draw a logic to distribute clock for minimal clock latencies in various blocks of SOC |
| How to minimize clock jitter |
| How to reduce clock latency |
| How clock gating works |
| How to achieve 180 degrees phase shift |
| Clock skew? How to reduce clock skew? |
| What is glitch? What causes it (explain with waveform)? How to overcome it? |
| Active low and active high |
| Why interrupts are active low |
| PISO, SIPO |
| How do we achieve multiply and division using register shift |
| How to achieve multiple by 3 using shift? |
| Comparator |
| Write gate logic to compare 2 8-bit signals |
| Difference between full substractor and half substractor |
| Implement full substractor from full adder |
| Digital design interview questions |
| The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotation. |
| You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and second is “ripple” (cascading), Which circuit has a less propagation delay? Why? |
| Design a circuit for finding the 9’s complement of a BCD number using 4-bit binary adder and some external logic gates? |
| Design a circuit that calculates square of a number |
| CRC calculation logic |
| Logic diagram |
| Pattern detector FSM |
| Give the circuit to extend the falling edge of the input by 2 clock pulses? |
| Circuit design for various requirements |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Course Highlights
- Mentor Support for doubt clarifications
- Product company focused questions
- 49 hours of lectures
TESTIMONIALS
What Our Students Says About Inskill
VLSIGURU training institute is one of the best training institute for VLSI domain.
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I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I recently completed the Functional Verification course at VLSIGuru, and I must say it was an exceptional training experience.
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The instructors were highly knowledgeable and provided clear explanations,making complex concepts easy to understand.
The practical hands-on exercises and real-world examples greatly enhanced my learning and problem-solving skills.
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Overall, VLSIGuru's Functional Verification course has equipped me with the necessary skills and confidence to excel in the field.
Highly recommended!
I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
FAQ
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