AMBA(AXI, AHB, APB) Protocol and AXI, AHB, APB UVC Development Training

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AMBA(AXI, AHB, APB) Protocol and AXI, AHB, APB UVC Development Training

  • Course Duration: 53 Hours
  • 4.6 Star (Rating)
  • 500+ (Student Enrolled till Now)
About Course

AMBA Protocol elearning course is a 28 hours course structured to enable participants gain expertise in AXI4.0, AHB5 and APB protocols. AMBA protocol knowledge is one of the most sought after skillset in any design and verification engineer. Majority of designs are based on ARM architecture, hence they are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have in depth knowledge of these protocols. SoC design debug and testbench component coding in most cases involves AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.

AMBA Protocol elearning course focuses on protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB5 and APB. Course also focus on protocol UVC and VIP development from scratch.

Demo Videos

Unit NumberTopicDuration(MIns)
1AXI Protocol introduction206
2AXI Protocol features110
3AXI Protocol advanced features103
4AXI Protocol advanced features65
5VIP development concepts, VIP template coding45
6VIP BFM and Generator coding, Testcase development98
7VIP monitor and coverage coding, Coverage report analysis161
8Reference model and checker coding161
9Assertions coding, Advanced feature implementation83
10AXI advanced feature implementation, Slave implementation as a slave VIP60
11AXI advanced feature checking25
12AXI UVC Development68
13AXI Scoreboard coding - 2 different styles183
14UVC-integration-into-TB8
15AXI Scoreboard integration steps6
16AXI, AHB interview questions4
17AXI Interconnect development concepts6
18AXI WRAP FIXED Burst Implementation concepts53
19AMBA training overview (watch before starting the course)2
20APB SES1 - APB protocol overview39
21APB SES2 - APB UVC and TB template development44
22APB UVC sequence and test case coding and debug66
23AHB protocol basics19
24AHB Basics, AHB system architecture15
25AHB transfer phases16
26AHB protocol handshaking7
27Arbitration phase14
28AHB transfer timing diagrams31
29Signal decoding26
30AHB transaction example10
31Burst transfers16
32AHB features, aligned transfers, wrap transfers58
33Questions, revision32
34Features: Address decoding15
35AHB master signals20
36AHB features: Early burst termination8
37Two cycle response8
38AHB arbitration, Split, retry28
39Exclusive transfers17
40AHB UVC: Type of UVC, TB Development using UVC18
41AHB UVC template development50
42AHB UVC functional development13
43Revision, questions, AHB transaction coding advanced aspects50
44AHB Driver coding69
45AHB Responder coding32
46AHB monitor coding36
47AHB interface coding43
48Revision, AHB responder update, AHB UVC issue summary33
49Doubt Clarification8
50AHB UVC issue debugging112
51AHB Sequence review15
52AHB UVC scoreboard33
53Assertions16
54Implementing testcases30
55AHB interview questions15
56Revision, AHB interconnect SOC and IP level verification overview12
57UVC-integration-into-TB8
58AHB interconnect verification212
59Sequence library212
60Revision, AHB I/C feature listing down20
61AHB scoreboard110
62Batch AHB UVC60
63BatchAHB LITE UVC Development26
64Batch AHB protocol: Round robin priority, start_item, finish_item6

 

Curriculum

On-chip protocols
Peripheral protocols
Importance of AMBA protocols for VLSI engineer?
APB protocol basics
Features
APB system architecture
Signal descriptions
APB transaction state diagram
AXI Protocol features
AMBA protocol overview
ARM processor - categories
AMBA Protocol basics
Comparison of APB, AHB and AXI protocols.
Correlating AXI with APB protocol
Features added in AXI on top of APB protocol
SOC Architecture - Significance of AXI protocol
AXI architecture components
How five channels help AXI protocol?
Write & Read Channels
AXI Channel handshaking
Write Channel Signals - Address, Data and Response
Read Channel Signals - Address and Data
Ports added in AXI protocol
Write Transaction Timing Diagram
How to draw timing diagrams?
Read Transaction Timing Diagram
Big endian and little-endian architecture
Wrap write and read transactions
Narrow transfers
Data bus and strobe relation
Responses in AXI
Locked and exclusive transfers
Aligned and unaligned transfers
Overlapping, out of order, interleaved txs
Interconnect role in out of order transaction
Significance of ID in AXI protocol
AXI Channel handshake dependency
Cacheable and bufferable transactions
Protected transactions
New ports added
Memory attributes signalling
Modifiable transactions
Non-modifiable transactions
Read-allocate and write-allocate
Memory types
Transaction buffering
QOS signalling
Multiple region signalling
User-defined signalling
Need for UVC?
Different types of UVC’s
Active
Master
Slave
Passive
UVC usage in module and SOC verification
Where Passive UVC are used?
UVC integration into TB
AXI UVC architecture
AXI Transaction Definition
AXI UVC component coding
Driver, sequencer, monitor, coverage
Environment, interface, slave model
Transaction, assertions
AXI UVC integration
AXI scoreboard coding
UVC integration in SOC TB
Testcase and sequence coding
Waveform analysis
Assertion coding and analysis
Functional coverage analysis
AHB and AXI: How they differ?
AHB based system architecture
AHB transfers: Various phases
Arbitration Phase
Address Phase
Data Phase
Burst transfers
Aligned transfers
Narrow transfers
Incrementing and wrapping transactions
Exclusive transfers
Exclusive access monitor
Exclusive Access signaling
Exclusive transfer restrictions
Resp signal
Two cycle response
Split and retry responses
UVC architecture
UVC components
UVC types
Master, slave
Active, Passive
UVC test case listing down
UVC component coding
Driver, sequencer, monitor, coverage
Environment, interface, slave model
Transaction, assertions
UVC Component integration
Sequence and test case development
Simulations, waveform analysis
Functional coverage analysis
Assertion coding and analysis

Benefits of eLearning?
  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹9,500 + GST

₹10,600    (10% Off)

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Course Highlights

  • 1-1 mentor support
  • Mentor guidance support for assignments
  • Multiple mock interviews
  • Dedicated live support sessions over weekends
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TESTIMONIALS

What Our Students Says About Inskill

Naga Sai Krishna Merugumilli
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One of the best training institute in Bangalore. We can experience the quality of training. The way they are responding to every problem. Best trainers are there to teach.

7 Days Ago
Manjush Padmamma Venkatesha
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The training I received here for SystemVerilog was one of the best.
It helped me out in a long run in better understanding language usage for Design Verification during my Master's program, as well as to crack most of my interviews.

The small projects I worked upon here, did helped me a lot for my Masters and on the other side did improved my skills.

In a single word, I can put up like, I got my basics right!!!!:)

I was really happy with the way the Institute has structured the course to help students to figure out their own way to improvise one's skills. Thank you for all your immense support.
Keep up the good work:)

10.04.2018
Harish kumar
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Best place to start your career in vlsi domain.
They act as bridge to help students to get industry requirements for the job.
Interms of teaching they are excellent for what we paid and get less fees compared to other institutions.
Even after course completion also they support if u had any doubts

5 Month Ago
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Doctor
Mani Shankar
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Best Platform for VLSI DOMAIN. The Faculty is friendly.
In videos Srinivas Sir is the best in teaching.
The Lab Session are very very Good They will clear your all the doubts.
They Conduct PPT presentations Session for students for real experience and
Mock iAnd thanks to srinivas Reddy sir and monahar sir to solve my issuenterviews
And thanks to srinivas Reddy sir and monahar sir to solve my issue.

6 Month Ago

FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

  1. Exposure to any bus protocols like I2C, SPI, etc
  2. Exposure to digital design concepts

Yes. Participant will gain exposure to following aspects

  1. VIP development for AXI3 protocol
  2. UVC development for APB protocol
  3. Analysing AXI, AHB and APB timing diagrams in simulations
  4. Functional coverage analysis
  5. Assertion coding and debugging

Each session of course is recorded, missed session videos will be shared

  1. Yes, You will have option to view the recorded videos of course for the sessions missed
  2. You will have option to repeat the course any time in next 1 year

  1. Yes, Course fee also includes support for doubt clarification sessions even after course completion
  2. You have option to mail you queries
  3. Option to meet in person to clarify doubts