AMBA(AXI, AHB, APB) Protocol and AXI, AHB, APB UVC Development Training
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AMBA(AXI, AHB, APB) Protocol and AXI, AHB, APB UVC Development Training
- Course Duration: 53 Hours
- 4.6 Star (Rating)
- 500+ (Student Enrolled till Now)
About Course
AMBA Protocol elearning course is a 28 hours course structured to enable participants gain expertise in AXI4.0, AHB5 and APB protocols. AMBA protocol knowledge is one of the most sought after skillset in any design and verification engineer. Majority of designs are based on ARM architecture, hence they are based on AMBA protocols(AXI, AHB and APB), which makes it essential for every design & verification engineer to have in depth knowledge of these protocols. SoC design debug and testbench component coding in most cases involves AXI and/or AHB protocols, and also majority of interviews are focused on candidate familiarity with AXI or AHB protocol. All this makes it essential for every VLSI engineer to have good working knowledge of these protocols.
AMBA Protocol elearning course focuses on protocol concepts, features, timing diagrams from basic to advanced for AXI4.0, AHB5 and APB. Course also focus on protocol UVC and VIP development from scratch.
Demo Videos
| Unit Number | Topic | Duration(MIns) |
| 1 | AXI Protocol introduction | 206 |
| 2 | AXI Protocol features | 110 |
| 3 | AXI Protocol advanced features | 103 |
| 4 | AXI Protocol advanced features | 65 |
| 5 | VIP development concepts, VIP template coding | 45 |
| 6 | VIP BFM and Generator coding, Testcase development | 98 |
| 7 | VIP monitor and coverage coding, Coverage report analysis | 161 |
| 8 | Reference model and checker coding | 161 |
| 9 | Assertions coding, Advanced feature implementation | 83 |
| 10 | AXI advanced feature implementation, Slave implementation as a slave VIP | 60 |
| 11 | AXI advanced feature checking | 25 |
| 12 | AXI UVC Development | 68 |
| 13 | AXI Scoreboard coding - 2 different styles | 183 |
| 14 | UVC-integration-into-TB | 8 |
| 15 | AXI Scoreboard integration steps | 6 |
| 16 | AXI, AHB interview questions | 4 |
| 17 | AXI Interconnect development concepts | 6 |
| 18 | AXI WRAP FIXED Burst Implementation concepts | 53 |
| 19 | AMBA training overview (watch before starting the course) | 2 |
| 20 | APB SES1 - APB protocol overview | 39 |
| 21 | APB SES2 - APB UVC and TB template development | 44 |
| 22 | APB UVC sequence and test case coding and debug | 66 |
| 23 | AHB protocol basics | 19 |
| 24 | AHB Basics, AHB system architecture | 15 |
| 25 | AHB transfer phases | 16 |
| 26 | AHB protocol handshaking | 7 |
| 27 | Arbitration phase | 14 |
| 28 | AHB transfer timing diagrams | 31 |
| 29 | Signal decoding | 26 |
| 30 | AHB transaction example | 10 |
| 31 | Burst transfers | 16 |
| 32 | AHB features, aligned transfers, wrap transfers | 58 |
| 33 | Questions, revision | 32 |
| 34 | Features: Address decoding | 15 |
| 35 | AHB master signals | 20 |
| 36 | AHB features: Early burst termination | 8 |
| 37 | Two cycle response | 8 |
| 38 | AHB arbitration, Split, retry | 28 |
| 39 | Exclusive transfers | 17 |
| 40 | AHB UVC: Type of UVC, TB Development using UVC | 18 |
| 41 | AHB UVC template development | 50 |
| 42 | AHB UVC functional development | 13 |
| 43 | Revision, questions, AHB transaction coding advanced aspects | 50 |
| 44 | AHB Driver coding | 69 |
| 45 | AHB Responder coding | 32 |
| 46 | AHB monitor coding | 36 |
| 47 | AHB interface coding | 43 |
| 48 | Revision, AHB responder update, AHB UVC issue summary | 33 |
| 49 | Doubt Clarification | 8 |
| 50 | AHB UVC issue debugging | 112 |
| 51 | AHB Sequence review | 15 |
| 52 | AHB UVC scoreboard | 33 |
| 53 | Assertions | 16 |
| 54 | Implementing testcases | 30 |
| 55 | AHB interview questions | 15 |
| 56 | Revision, AHB interconnect SOC and IP level verification overview | 12 |
| 57 | UVC-integration-into-TB | 8 |
| 58 | AHB interconnect verification | 212 |
| 59 | Sequence library | 212 |
| 60 | Revision, AHB I/C feature listing down | 20 |
| 61 | AHB scoreboard | 110 |
| 62 | Batch AHB UVC | 60 |
| 63 | BatchAHB LITE UVC Development | 26 |
| 64 | Batch AHB protocol: Round robin priority, start_item, finish_item | 6 |
Curriculum
| Introduction to on-chip protocols |
| Protocol overview |
| AXI revisions |
| AXI based system architecture |
| Global signals |
| Write address channel signals |
| Write data channel signals |
| Write response channel signals |
| Read address channel signals |
| Read data channel signals |
| Low power interface signals |
| Basic write and read transactions |
| Relationship between channels |
| Transaction structure |
| Transaction types and attributes |
| AXI3 memory attribute signalling |
| AXI4 changes to memory attribute signalling |
| Memory types |
| Mismatched memory attributes |
| Transaction buffering |
| Access permissions |
| AXI transaction identifiers |
| Transaction ID |
| Transaction ordering |
| Definition of ordering model |
| Master ordering |
| Interconnect ordering |
| Slave ordering |
| Response before final destination |
| Single-copy atomicity size |
| Exclusive accesses |
| Locked accesses |
| Atomic access signaling |
| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
| Low power interface signals |
| Low power clock control |
| Interoperability principles |
| Major Interface categories |
| Default signal values |
| VIP architecture |
| VIP components |
| VIP types |
| Master, Slave |
| Active, Passive |
| VIP test scenario listing down |
| VIP component coding |
| Driver, Generator, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
| Enhance AXI3 VIP for AXI4 additional features |
| QoS signaling |
| Multiple region signaling |
| User-defined signaling |
| Low power interface |
| Introduction |
| About the protocol |
| AHB revisions |
| Operation |
| Signal Descriptions |
| Global signals |
| Master signals |
| Slave signals |
| Decoder signals |
| Multiplexor signals |
| Transfers |
| Basic transfers |
| Transfer types |
| Locked transfers |
| Transfer size |
| Burst operation |
| Waited transfers |
| Protection control |
| Memory types |
| Secure transfers |
| Bus Interconnection |
| Interconnect |
| Address decoding |
| Read data and response multiplexor |
| Slave Response Signaling |
| Slave transfer responses |
| Data Buses |
| Data buses |
| Endianness |
| Data bus width |
| Clock and Reset |
| Clock and reset requirements |
| Exclusive Transfers |
| Introduction |
| Exclusive Access Monitor |
| Exclusive access signaling |
| Exclusive Transfer restrictions |
| Atomicity |
| Single-copy atomicity size |
| Multi-copy atomicity |
| User Signaling |
| User signal description |
| User signal interconnect recommendations |
| UVC architecture |
| UVC components |
| UVC types |
| Master, Slave |
| Active, Passive |
| UVC test scenario listing down |
| UVC component coding |
| Driver, Sequencer, Monitor, Coverage, Environment |
| Interface, transaction, Slave model, assertions |
| Testbench integration |
| Testcase coding |
| Simulations and waveform analysis |
| Functional coverage analysis |
| Assertion coding and analysis |
| APB protocol introduction |
| Signal descriptions |
| Transfers |
| Operating states |
| Develop APB UVC for master and slave |
| APB master UVC validation using slave UVC |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Dedicated Trainer Accessible On Phone / Email / Whatsapp
- Trainer Exp: 15 Years
Price - ₹9,500 + GST
₹10,600 (10% Off)
10 hours left to avail at this price
Course Highlights
- Mentor Support for doubt clarifications
- Product company focused questions
- 49 hours of lectures
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FAQ
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