SPI Protocol and UVC Development Training
SPI Protocol training is focused on learning all the aspects of SPI including architecture, signals, transactions, features, etc.
- 6 HoursCourse Duration
- 2 SessionsRecorded & Live
- 4.6/5Learner Rating
- 100+Enrolled Learners
Course Overview
About Course
SPI Protocol training is focused on learning all the aspects of SPI including architecture, signals, transactions, features, etc. SPI UVC development is focused on developing SPI master UVC and SPI slave UVC. SPI master and slave UVC are validated by connecting each other. This also involves developing scoreboard and checking for checking test case passing.
Detailed Syllabus
2 modules- Introduction
- Protocol overview
- SPI architecture
- Signal Descriptions
- SPI transactions
- Write
- Read
- Multiple slaves
- UVC architecture
- UVC components
- UVC types
- Master, Slave
- Active, Passive
- UVC test scenario listing down
- UVC component coding
- Driver, Sequencer, Monitor, Coverage, Environment
- Interface, transaction, Slave model, assertions
- Testbench integration
- Testcase coding
- Simulations and waveform analysis
- Functional coverage analysis
- Assertion coding and analysis
Session-wise Content
2 sessions · 5h 14m- 1SPI PROTOCOL, SPI Controller RTL, SPI verification using Verilog2h 58m
- 2SPI UVC Development2h 16m
Your Instructor
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to any bus protocols like I2C, SPI, etc
- Exposure to digital design concepts
Yes. Participant will gain exposure to following aspects
- VIP development for AXI3 protocol
- UVC development for AHB2 protocol
- UVC development for APB protocol
- Analysing AXI, AHB and APB timing diagrams in simulations
- Functional coverage analysis
- Assertion coding and debugging
Each session of course is recorded, missed session videos will be shared
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts