DFT Training
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DFT Training
- Course Duration: 119 Hours
- 4.8 Star (Rating)
- 20000+ (Student Enrolled till Now)
About Course
DFT Training – Design for Testability Course (Scan, ATPG, JTAG, MBIST)
Design for Testability (DFT) involves using advanced test techniques such as Scan, ATPG, JTAG, MBIST, LBIST and Test Compression to improve hardware testability. These techniques are essential for identifying manufacturing defects like stuck-at faults, transition delay faults, path delay faults, and other structural defects in ASIC and SoC designs.
This industry-oriented DFT Training course is designed to provide in-depth exposure to complete DFT flow, Scan architecture, ATPG pattern generation, Debug methodologies, and Diagnosis techniques used in semiconductor companies.
What You Will Learn in DFT Training
- DFT fundamentals and testability concepts
- Different fault models: Stuck-at, Transition Delay, Path Delay faults
- SoC Scan Architecture and various Scan types
- Scan insertion and Hierarchical Scan Design
- ATPG DRC Debug and ATPG Simulation Debug
- Test Compression techniques (TestKompress)
- DFT Diagnosis methodologies
- JTAG (Boundary Scan) architecture and applications
- Memory BIST (MBIST) and Logic BIST (LBIST)
Hands-On DFT Practical Training
As part of the training, students will work on a complex SoC design example with multiple embedded memories. Practical sessions include:
- Scan chain insertion and validation
- MBIST controller integration and memory testing
- Boundary Scan (JTAG) implementation
- ATPG pattern generation for different fault models
- Test pattern compression using TestKompress
- Pattern validation through simulations
Compressed test patterns reduce IO usage, minimize tester memory requirements, and improve production test efficiency.
Tool-Based Training – Mentor Graphics Tessent
The course uses Mentor Graphics Tessent Tool, one of the most widely adopted DFT tools in the semiconductor industry. Industry surveys indicate that Tessent is used by more than 80% of leading semiconductor companies.
Students will gain practical exposure to:
- Scan insertion using Tessent
- ATPG pattern generation and coverage analysis
- ATPG debug and fault simulation
- Compression setup and validation
Students will have access to the Tessent tool at the institute for 12 months after course completion, with an option to extend access.
Who Should Enroll?
- VLSI freshers aiming for DFT Engineer roles
- RTL Design engineers transitioning to DFT
- Verification engineers exploring Test Engineering
- Working professionals upgrading DFT tool skills
This DFT Training ensures strong conceptual clarity, extensive hands-on experience, and industry-ready expertise in Scan, ATPG, JTAG, MBIST, and Test Compression methodologies.
Demo Videos
| Unit Number | Topic | Duration (Mins) |
| 1 | What is DFT Manufacturing Defects, Why Testing Major Challenges in DFT | 52 |
| 2 | Fault Models, Types of Test Logic Insertion | 41 |
| 3 | Assignment Questions | 18 |
| 4 | Difference between pin, port and pad & clock gating | 39 |
| 5 | Disadvantages of clock gating cell (and gate), Integrated clock gating cell (ICG) | 25 |
| 6 | Need of DFT | 47 |
| 7 | Yield, Defect, Fault and error & DFT architecture | 73 |
| 8 | Scan Insertion | 69 |
| 9 | Calculating over all Test time post scan insertion | 21 |
| 10 | Full sacn vs Partial scan, Types of scan cells | 51 |
| 11 | Comparision of various scan cells, Scan chain operation | 42 |
| 12 | Problems with scan designs | 22 |
| 13 | Clock controllability DRC | 115 |
| 14 | Assignment answers discussions | 24 |
| 15 | Reset controllability DRC | 26 |
| 16 | Tristate buffer DRC, potential race condition | 44 |
| 17 | X source DRC, Feedback loop DRC | 30 |
| 18 | Deciding the no.of scan chains and scan chain length | 23 |
| 19 | Bus contention, Top down apprach, Bottom up appraoch | 27 |
| 20 | Inputs and outputs of scan, Scan chain reorder | 56 |
| 21 | Edge mixing and domain mixing | 46 |
| 22 | Practical Explanation of scan insertion | 25 |
| 23 | Pre-existing scan chains | 22 |
| 24 | Scan compression and its need | 87 |
| 25 | Decompressor, Compression ratio, Compressor | 18 |
| 26 | Bypass, Pipeline flops in compressor | 63 |
| 27 | EDT waveform, masking logic | 29 |
| 28 | Lock up latches, EDT insertions in hierarchical scan | 23 |
| 29 | EDT DRCs | 20 |
| 30 | Methods to fix DRCs, ATPG introduction | 38 |
| 31 | D algorithm | 8 |
| 32 | Other algorithms, Fault model | 29 |
| 33 | Fault categories | 40 |
| 34 | Coverage, Untestable faults, Flow of ATPG | 46 |
| 35 | Fault classes | 55 |
| 36 | ATPG Untestable (AU) class | 62 |
| 37 | Other AU faults, Untestable faults | 11 |
| 38 | Assignment answers discussion and doubt clarrifications | 30 |
| 39 | Patterns classification chain, serial, parallel | 16 |
| 40 | Pattern classification (based on format and category) | 73 |
| 41 | ATPG practicals | 33 |
| 42 | Simulations | 46 |
| 43 | Practicals of ATPG TDF and simulations | 87 |
| 44 | Simulation mismatch debug | 36 |
| 45 | Doubt clarifications, Assignment questions | 27 |
| 46 | OCC part 1 | 67 |
| 47 | OCC part 2 | 12 |
| 48 | Doubt clarification and assignment discussions | 12 |
| 49 | Doubt clarification, Assignment discussions | 63 |
| 50 | ATPG IDDQ theory | 8 |
| 51 | IDDQ lab | 17 |
| 52 | Path Delay Fault Model (PDF) | 53 |
| 53 | JTAG introduction, Boundary Scan | 20 |
| 54 | Instructions (Mandatory + Optional) | 17 |
| 55 | JTAG network, comparison between various standards | 20 |
| 56 | BSDL | 33 |
| 57 | Assignment answers discussion | 21 |
| 58 | JTAG TAP architecture | 58 |
| 59 | JTAG TAP Controller (16 state FSM) | 23 |
| 60 | Memory Basics, Memory architecture | 16 |
| 61 | Memory Faults | 52 |
| 62 | Memory Faults (Contd...) | 15 |
| 63 | Zero-One algorithm and Checkerboard algorithm | 14 |
| 64 | March Algorithms (MATS, MATS+, MATS++, MarchX, March C) | 28 |
| 65 | Algorithms supported by mentor tools | 56 |
| 66 | Tessent MBIST | 25 |
| 67 | Comparision between JTAG and IJTAG | 29 |
| 68 | TSDB flow explanation | 80 |
| 69 | Lab MBIST insertion | 66 |
| 70 | TSDB output directory explanation, MBIST simulations | 58 |
| 71 | Lab | 64 |
| 72 | Scan Wrappers | 84 |
| 73 | Lab3 (MBIST, EDT OCC insertion) | 21 |
| 74 | Lab3 (Scan, ATPG, Simulation, MBIST patterns on netlist) | 21 |
| 75 | Lab4 (MBIST, EDT OCC insertion) | 37 |
| 76 | Lab4 remaining topics | 50 |
| 77 | Level 4 projects THY | 50 |
Curriculum
| ASIC & VLSI Design Flow |
| Session covering complete flow overview from product requirements to Post silicon validation. |
| Advanced Digital Design |
| 2 weeks dedicated course focusing on all aspects of Digital design. |
| www.vlsiguru.com/digital-design-complete |
| Verilog programming basics |
| 3 Weeks of Verilog training covering all the aspects of Verilog required for DFT engineer |
| This course is done in parallel with Advanced Digital design course |
| Linux OS |
| 1 week training on Linux OS and hands on |
| TCL Scripting |
| 1 week training on TCL scripting for flow automation |
| DFT Basics |
| SoC Scan architecture overview |
| Types of Scan |
| ATPG DRC Debug |
| ATPG Simulation Mismatch Debug |
| JTAG |
| MemoryBIST |
| Scan and ATPG |
| Test compression technigues |
| Hierarchical Scan Design |
| Full SOC flow - DFT |
| DFT Architecture and Basics |
| Test Plan |
| Different DFT schemes |
| Comparison between Functional and DFT Vectors |
| Understanding of SCAN Insertion |
| Scan methodology |
| Types of Scan |
| Top-down and Bottom-up Approach |
| Scan insertion Flow |
| Scan insertion Scripts |
| Multiple Clock domains |
| Design Rule Checking |
| Pre-DRC and Post DRC |
| Lock up and Terminal lockup latches |
| Hands-on Scan insertion |
| Assignments |
| Introduction to compression |
| Compression Architecture |
| Decompressor and Compactor |
| Compression Ratio |
| DRC Analysis |
| Modular Compression |
| X-Masking logic |
| Hands-on Compression |
| Assignments |
| Scan insertion with compression |
| On-chip clocking for at-speed testing |
| Hierarchical Scan Design |
| Bypass mode |
| Hands on Scan and compression |
| Interaction session scan and compression |
| Memory faults |
| Algorithms |
| Diagnostic mode |
| ATPG Overview |
| Different types of Faults |
| Types of fault models |
| DRC analysis |
| Test Coverage and Fault Coverage |
| Coverage improvement Analysis |
| Chain and Capture patterns |
| Assignments |
| Simulations- No-timing |
| At speed fault model (In detail) |
| Understanding Transition fault ATPG |
| Two pulse generator |
| Test procedure |
| Launch on capture and Launch on Shift |
| Top-off Pattern generation |
| Path delay |
| Introduction to JTAG |
| JTAG State Machine |
| Boundary Scan |
| Different instructions |
| Industry Standard Project |
| Revision |
| Mock Interview |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Sreenivas Reddy — Founder, VLSIGuru
Course Highlights
- 1-1 mentor support
- Mentor guidance support for assignments
- Multiple mock interviews
- Dedicated live support sessions over weekends
TESTIMONIALS
What Our Students Says About Inskill
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I recently completed the Functional Verification course at VLSIGuru, and I must say it was an exceptional training experience.
The course content was comprehensive, covering all essential aspects of functional verification.
The instructors were highly knowledgeable and provided clear explanations,making complex concepts easy to understand.
The practical hands-on exercises and real-world examples greatly enhanced my learning and problem-solving skills.
The course structure was well-organized, allowing for a smooth progression from fundamentals to advanced topics.
Overall, VLSIGuru's Functional Verification course has equipped me with the necessary skills and confidence to excel in the field.
Highly recommended!
I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
FAQ
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
Institute is driven by philosophy of ‘Quality education at affordable fee’. Education should be affordable to majority of the people. Even otherwise basic courses like Digital Design, Verilog, SV, UVM, UNIX and Scripting all together can’t cost 1 lakh+. These are just languages and some projects.
- Basic exposure to digital design concepts
Design for Testability is a methodology used to make semiconductor chips easier to test after manufacturing. It improves defect detection by inserting additional logic such as scan chains and test controllers during the design phase.
Modern chips are highly complex, and manufacturing defects can impact functionality. DFT techniques help identify structural faults early, reduce test costs, and improve product reliability before chips are shipped to customers.
The course covers Scan insertion, ATPG pattern generation, Boundary Scan (JTAG), Memory BIST, Logic BIST, compression techniques, and hierarchical scan architecture.
Yes. The training includes hands-on practice using Mentor Graphics Tessent, a widely adopted tool for test insertion, ATPG, and coverage analysis.
Yes. The program starts with fundamentals and gradually moves to advanced topics. It is designed to prepare fresh graduates for entry-level roles in semiconductor companies.
Absolutely. Engineers from RTL, verification, or non-VLSI backgrounds can enroll to transition into test engineering roles.
Students work on a complex design example that includes multiple memory blocks. Practical sessions involve scan chain implementation, compression setup, fault simulation, and pattern validation.
Basic knowledge of digital design is helpful but not mandatory. The course includes foundational concepts required for understanding test insertion flow.
You can apply for positions such as Test Engineer, DFT Engineer, ATPG Engineer, or SoC Test Engineer in semiconductor companies.
While digital design focuses on building functionality, this program emphasizes making hardware testable and validating it after fabrication.
Yes. The course covers different structural fault models including stuck-at, transition delay, and path delay faults.