DFT Training

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DFT Training

About Course

DFT(Design for Testability) involves using SCAN, ATPG, JTAG and BIST techniques to add testability to the Hardware design. These techniques are targeted for developing and applying tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, and transition delay faults etc.

DFT Training will focus on all aspects of testability flow including DFT basics, various fault types, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests. ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.
DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG, JTAG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression, JTAG and ATPG pattern generation using Tessent tool. More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.
MentorGraphics Tessent tool is used for training. As per industry survey, it is used by more than 80% companies for DFT. Student will have access to tool at the institute for 12 months after course completion, with a provision to extend beyond.

Demo Videos

Unit Number	Topic	Duration (Mins)
1	What is DFT Manufacturing Defects, Why Testing Major Challenges in DFT	52
2	Fault Models, Types of Test Logic Insertion	41
3	Assignment Questions	18
4	Difference between pin, port and pad & clock gating	39
5	Disadvantages of clock gating cell (and gate), Integrated clock gating cell (ICG)	25
6	Need of DFT	47
7	Yield, Defect, Fault and error & DFT architecture	73
8	Scan Insertion	69
9	Calculating over all Test time post scan insertion	21
10	Full sacn vs Partial scan, Types of scan cells	51
11	Comparision of various scan cells, Scan chain operation	42
12	Problems with scan designs	22
13	Clock controllability DRC	115
14	Assignment answers discussions	24
15	Reset controllability DRC	26
16	Tristate buffer DRC, potential race condition	44
17	X source DRC, Feedback loop DRC	30
18	Deciding the no.of scan chains and scan chain length	23
19	Bus contention, Top down apprach, Bottom up appraoch	27
20	Inputs and outputs of scan, Scan chain reorder	56
21	Edge mixing and domain mixing	46
22	Practical Explanation of scan insertion	25
23	Pre-existing scan chains	22
24	Scan compression and its need	87
25	Decompressor, Compression ratio, Compressor	18
26	Bypass, Pipeline flops in compressor	63
27	EDT waveform, masking logic	29
28	Lock up latches, EDT insertions in hierarchical scan	23
29	EDT DRCs	20
30	Methods to fix DRCs, ATPG introduction	38
31	D algorithm	8
32	Other algorithms, Fault model	29
33	Fault categories	40
34	Coverage, Untestable faults, Flow of ATPG	46
35	Fault classes	55
36	ATPG Untestable (AU) class	62
37	Other AU faults, Untestable faults	11
38	Assignment answers discussion and doubt clarrifications	30
39	Patterns classification chain, serial, parallel	16
40	Pattern classification (based on format and category)	73
41	ATPG practicals	33
42	Simulations	46
43	Practicals of ATPG TDF and simulations	87
44	Simulation mismatch debug	36
45	Doubt clarifications, Assignment questions	27
46	OCC part 1	67
47	OCC part 2	12
48	Doubt clarification and assignment discussions	12
49	Doubt clarification, Assignment discussions	63
50	ATPG IDDQ theory	8
51	IDDQ lab	17
52	Path Delay Fault Model (PDF)	53
53	JTAG introduction, Boundary Scan	20
54	Instructions (Mandatory + Optional)	17
55	JTAG network, comparison between various standards	20
56	BSDL	33
57	Assignment answers discussion	21
58	JTAG TAP architecture	58
59	JTAG TAP Controller (16 state FSM)	23
60	Memory Basics, Memory architecture	16
61	Memory Faults	52
62	Memory Faults (Contd...)	15
63	Zero-One algorithm and Checkerboard algorithm	14
64	March Algorithms (MATS, MATS+, MATS++, MarchX, March C)	28
65	Algorithms supported by mentor tools	56
66	Tessent MBIST	25
67	Comparision between JTAG and IJTAG	29
68	TSDB flow explanation	80
69	Lab MBIST insertion	66
70	TSDB output directory explanation, MBIST simulations	58
71	Lab	64
72	Scan Wrappers	84
73	Lab3 (MBIST, EDT OCC insertion)	21
74	Lab3 (Scan, ATPG, Simulation, MBIST patterns on netlist)	21
75	Lab4 (MBIST, EDT OCC insertion)	37
76	Lab4 remaining topics	50
77	Level 4 projects THY	50

Curriculum

1 : VLSI Basics Course (WEEK#1 to WEEK#5)

ASIC & VLSI Design Flow

Session covering complete flow overview from product requirements to Post silicon validation.

Advanced Digital Design

2 weeks dedicated course focusing on all aspects of Digital design.

www.vlsiguru.com/digital-design-complete

Verilog programming basics

3 Weeks of Verilog training covering all the aspects of Verilog required for DFT engineer

This course is done in parallel with Advanced Digital design course

Linux OS

1 week training on Linux OS and hands on

TCL Scripting

1 week training on TCL scripting for flow automation

2 : WEEK#6 : Design For Testability Basics

DFT Basics

SoC Scan architecture overview

Types of Scan

ATPG DRC Debug

ATPG Simulation Mismatch Debug

DFT Diagnosis

JTAG

MemoryBIST

LogicBIST

Scan and ATPG

Test compression technigues

Hierarchical Scan Design

3 : Week-7

Full SOC flow - DFT

DFT Architecture and Basics

Test Plan

Different DFT schemes

Comparison between Functional and DFT Vectors

4 : Week-8

Understanding of SCAN Insertion

Scan methodology

Types of Scan

Top-down and Bottom-up Approach

Scan insertion Flow

5 : Week-9

Scan insertion Scripts

Multiple Clock domains

Design Rule Checking

Pre-DRC and Post DRC

Lock up and Terminal lockup latches

Hands-on Scan insertion

Assignments

6 : Week-10

Introduction to compression

Compression Architecture

Decompressor and Compactor

Compression Ratio

DRC Analysis

7 : Week-11

Modular Compression

X-Masking logic

Hands-on Compression

Assignments

8 : Week-12

Scan insertion with compression

On-chip clocking for at-speed testing

Hierarchical Scan Design

Bypass mode

Hands on Scan and compression

Interaction session scan and compression

9 : Week-13

Memory faults

Algorithms

Diagnostic mode

10 : Week-14

11 : Week-15

12 : Week-16

ATPG Overview

Different types of Faults

Types of fault models

13 : Week-17

14 : Week-18

DRC analysis

Test Coverage and Fault Coverage

Coverage improvement Analysis

Chain and Capture patterns

Assignments

Simulations- No-timing and Timing simulations

15 : Week-19

At speed fault model (In detail)

Understanding Transition fault ATPG

Two pulse generator

Test procedure

Launch on capture and Launch on Shift

Top-off Pattern generation

Path delay

16 : Week-20

Introduction to JTAG

JTAG State Machine

Boundary Scan

Different instructions

Industry Standard Project

17 : Week-21

Introduction to LBIST

SPYGLASS

Revision

Mock Interview

Benefits of eLearning?

Access to the Instructor - Ask questions to the Instructor who taught the course
Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

Course Instructor

Dedicated Trainer Accessible On Phone / Email / Whatsapp
Trainer Exp: 15 Years

Price - ₹45,000 + GST

₹50,000 (10% Off)

10 hours left to avail at this price

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Course Highlights

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TESTIMONIALS

What Our Students Says About Inskill

Vishal Yadav

VLSIGuru is an exceptional educational institute for VLSI, providing comprehensive and up-to-date courses.The faculty at VLSIGuru possess deep expertise in VLSI design and deliver high-quality instruction to students.VLSIGuru's alumni network provides ongoing support and mentorship to current students, facilitating career growth. The fees of VLSIGURU Institute is very less as compared to other institutes.Early I had joined other Institute , fee of that Institute was so high and lectures was so less and they started direct cource without considering basic concepts. I left that Institute and joined VLSIGURU, and that was the best Desicision i always feel. VLSIGURU takes 2 months for basic cource and 4 months for advance which is good enough to build a deep knowledge in VLSI domain

7 Days Ago

Divyansh Mittal

I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.

The best thing about the institute is that the head of the institute teaches us one to one and make everything a cakewalk.
To be honest I didn't have any prior coding experience before
I am placed in Analog Devices Inclusive at very handsome package on Day 1 placements .
Thanks for the support.

10.04.2018

Vinutha M B

I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.

5 Month Ago

Amit V Ambaliya

I am very thankful to Owner of Vlsiguru institute Sreenivasa Reddy sir which have Excellent teaching skill and more powerful industry experience and good placement of these institute.
All mentor and trainer well experienced.

Verilog , system verilog ,UVM and project are in really depth with Lab and assignment session .

I appreciate efforts put up by all vlsiguru team and specially appreciate to Sreenivasa Reddy sir.

I strongly recommend this course for students who want to start their journey in vlsi domain.

THANKS A LOT TO VLSIGURU TRAINING INSTITUTE.

6 Month Ago

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