DDR Protocol Training

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DDR Protocol Training

About Course

Term DDR in resume opens up quite a few job opportunities!!..that is the importance of DDR in current SoC's..

DDR is an essential component of every complex SOC. It requires every engineer working on SoC to be well versed with DDR protocol concepts including DDR controller, DDR PHY, DDR memory, etc. The course focus on teaching DDR3, DDR4, timing diagrams, training sequence, DDR controller design concepts and DDRPHY concepts.

DDR2, DDR3, DDR4 Training

DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
DDR PHY basics
Architecture
Sub components
DDR Controller concepts

Demo Videos
Unit NumberTopicDuration (Mins)
1DDR technology training agenda7
2DDR significance in SOC, memory categories, SRAM versus DRAM, DRAM cell array86
3DDR memory organization74
4Rank, Channel, SIMM, DIMM, DDR evolution26
5DDR evolution, prefetch architecture, DDR frequently used terms39
6Interleaved access, wrapper architecture, control signals, timing parameters93
7Command truth table, SDR feature summary74
8DDR, DDR2, DDR3 feature summary85
9Latency and power consumption, DDR, DDR2, DDR3 feature comparison59
10DDR features, burst transfers40
11DDR addressing, Processor to DDR path19
12DDR mode registers, different write/read latency variables , DM, DQS, DDR initialization82
13SSTL active and passive termination21
14DDR commands, Refresh, DDR column access truth table82
15DDR timing diagrams, timing parameters71
16DDR pinout description (DDR to DDR4)53
17DDR wrapper pinout Description96
18DDR addressing (DDR to DDR4, LPDDR, LPDDR2)42
19LPDDR3, LPDDR4 Addressing21
20Mode registers : DDR, DDR234
21Mode registers - DDR3, DDR460
22Mode registers - LPDDR to LPDDR468
23State diagrams, power up initialization sequence : DDR to DDR4, LPDDR to LPDDR491
24DDR command truth table39
25Command truth table : DDR to DDR446
26Command truth table : LPDDR to LPDDR449
27DDR Verilog model simulations82
28DLL: Delay locked loop19
29OCD calibration, ZQ Calibration23
30Write levelling, Read levelling16
31ODT : On Die Termination57
32DDR Refresh: DDR1 to DDR4, LPDDR1 to LPDDR499
33DDR3 Feature summary, updates from DDR237
34DDR4 features, Feature updates from DDR373
35LPDDR Feature Summary: LPDDR1 to LPDDR47
36LPDDR1 features11
37LPDDR2 features35
38LPDDR3 features16
39LPDDR4 features58
40DDR Controller overview37
41DDR Controller functional verification concepts41
42DDR - RDIMM, LRDIMM8
43DDR PHY Interface (DFI)60
Curriculum

DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
LPDDR memory architecture, pages, banks, rows, columns
LPDDR bandwidth, transfer rate
LPDDR Interface signals
LPDDR commands, timing diagrams
LPDDR Mode registers
LPDDR clock frequency, limitation
LPDDR initialization and power up sequence
LPDDR Training: Write leveling, Read training, CA Training, ZQ Calibration
LPDDR use in SoC
Architecture
Sub components

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹7500 + GST

₹8,400    (10% Off)

10 hours left to avail at this price

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TESTIMONIALS

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FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

  1. Exposure to basic memory concepts like SRAM, FLash, etc
  2. Exposure to digital design concepts

  1. Dedicated sessions planned to train student on Protocol specific TB component coding

  1. Each session of course is recorded, missed session videos will be shared

  1. Yes, You will have option to view the recorded videos of course for the sessions missed
  2. You will have option to repeat the course any time in next 1 year

  1. Yes, Course fee also includes support for doubt clarification sessions even after course completion
  2. You have option to mail you queries
  3. Option to meet in person to clarify doubts