DDR Protocol Training

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DDR Protocol Training

About Course

Term DDR in resume opens up quite a few job opportunities!!..that is the importance of DDR in current SoC's..

DDR is an essential component of every complex SOC. It requires every engineer working on SoC to be well versed with DDR protocol concepts including DDR controller, DDR PHY, DDR memory, etc. The course focus on teaching DDR3, DDR4, timing diagrams, training sequence, DDR controller design concepts and DDRPHY concepts.

DDR2, DDR3, DDR4 Training

DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
DDR PHY basics
Architecture
Sub components
DDR Controller concepts

Demo Videos

Unit NumberTopicDuration (mins)
1DDR technology training agenda07:03
2SRAM, DRAM basics, DRAM cell array45:29
3DDR significance in SOC20:09
4DDR memory organization01:12:53
5Rank, Channel, SIMM, DIMM, DDR evolution25:18
6DDR evolution23:16
7DDR frequently used terms15:04
8DDR wrapper architecture15:40
9DDR wrapper signals35:17
10Interleaved and sequential access13:47
11SDR SDRAM features25:00
12Command truth table, Delay locked loop, DDR feature summary01:13:17
13DDR3 feature summary29:39
14DDR feature summary30:18
15DDR2 feature summary23:05
16DDR, DDR2, DDR3 feature comparison30:45
17Understanding latencies in DDR26:18
18DDR features, burst transfers #38:30
19DDR addressing, Processor to DDR path18:26
20DDR burst types - Sequential, Interleaved19:55
21DDR pinout description04:22
22DDR pinout description (DDR to DDR4)53:18
23LPDDR to LPDDR4 pin description53:13
24DDR4 pin description44:07
25Posted CAS and different write and read latency parameters09:27
26DDR core timing closure, DQS, DM32:23
27DDR initialization28:33
28Introduction to mode registers08:31
29SSTL active and passive termination20:57
30DDR commands, Auto precharge29:33
31DDR truth table different and same bank access, CKE truth table12:09
32Refresh - Self refresh, Auto refresh, tRFC, tRFI22:34
33DDR timing diagrams, timing parameters01:10:38
34DDR addressing (DDR to DDR4, LPDDR, LPDDR2)41:24
35LPDDR3, LPDDR4 Addressing20:54
36Mode registers : DDR, DDR234:00
37Mode registers - DDR3, DDR459:34
38Mode registers - LPDDR to LPDDR401:08:15
39DDR to DDR4 - State diagrams, power up initialization sequence01:05:43
40LPDDR to LPDDR4 - State diagrams, power up initialization sequence24:46
41DDR command truth table38:38
42Command truth table : DDR to DDR445:23
43Command truth table : LPDDR to LPDDR448:24
44Understanding DDR Verilog models01:16:10
45DDR Verilog model TB coding and analyzing simulation waveforms01:05:59
46DLL: Delay locked loop18:53
47OCD calibration11:03
48ZQ calibration11:35
49Write levelling, Read levelling15:34
50ODT : On Die Termination33:12
51Synchronous and Asynchronous ODT, Dynamic ODT22:59
52Auto and self Refresh: LPDDR to LPDDR431:14
53Auto and self Refresh: DDR1 to DDR401:07:17
54DDR3 Feature summary, updates from DDR236:55
55DDR4 features - Feature summary33:57
56DDR4 features - CRC09:54
57DDR4 features - CA Parity03:34
58DDR4 features - Control gear down mode06:29
59DDR4 features - Programmable preamble and postamble12:40
60DDR4 features - Connectivity test mode04:50
61LPDDR Feature Summary: LPDDR1 to LPDDR406:53
62LPDDR1 features10:18
63LPDDR2 features34:23
64LPDDR3 features15:28
65LPDDR4 features57:39
66DDR Controller overview36:48
67DDR Controller functional verification concepts40:11
68DDR - RDIMM, LRDIMM06:00
69DDR PHY Interface (DFI)01:00:02
Fee Structure
Curriculum

DDR memory architecture, pages, banks, rows, columns
DDR bandwidth, transfer rate
DDR Interface signals
DDR commands, timing diagrams
DDR Mode registers
DDR clock frequency, limitation
DDR initialization and power up sequence
DDR Training: Write leveling, Read training, CA Training, ZQ Calibration
DDR use in SoC
LP, PC DDR's
LPDDR memory architecture, pages, banks, rows, columns
LPDDR bandwidth, transfer rate
LPDDR Interface signals
LPDDR commands, timing diagrams
LPDDR Mode registers
LPDDR clock frequency, limitation
LPDDR initialization and power up sequence
LPDDR Training: Write leveling, Read training, CA Training, ZQ Calibration
LPDDR use in SoC
Architecture
Sub components

Benefits of eLearning?
  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years
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Course Highlights

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TESTIMONIALS

What Our Students Says About Inskill

FAQ

  1. Course presentations for all topics
  2. Session notes
  3. Lab documents with detailed steps
  4. User guides

  1. Exposure to basic memory concepts like SRAM, FLash, etc
  2. Exposure to digital design concepts

  1. Dedicated sessions planned to train student on Protocol specific TB component coding

  1. Each session of course is recorded, missed session videos will be shared

  1. Yes, You will have option to view the recorded videos of course for the sessions missed
  2. You will have option to repeat the course any time in next 1 year

  1. Yes, Course fee also includes support for doubt clarification sessions even after course completion
  2. You have option to mail you queries
  3. Option to meet in person to clarify doubts