PCIe Data link Layer UVC Development Training

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PCIe Data link Layer UVC Development Training

About Course

PCIe Data link layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and DLL-TL interface. These UVC are integrated with DLL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI, TL-DLL and DLL-PL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.

Demo Videos

Unit Number	Topic	Duration (Mins)
1	PCIe DLL course overview, features, course pre-requisites	29
2	DLL architecture	39
3	DLL design interfaces	11
4	Question: DLL buffer size	1
5	DLL design FSM and states	16
6	DLL RTL coding	43
7	PCIe DLL TB bringup	57
8	DLL TB development from scratch	78
9	Physical layer sequence library coding	69
10	Driver coding and DLL.SV design files updates	77
11	tl_item update	11
12	dll.sv and driver update for processing the TLP	88
13	TLP to link packet conversion, store LP to buffer	81
14	Fetching link packet from buffer and driving link packet to Physical layer	90
15	Physical layer agent collecting link packet, PL sequence library update to drive completion TLP	54
16	Memory write followed by memory read TLP	85
17	PL driver generate completion TLP in response to Memory read TLP	59
18	PL and TL agent monitor and coverage coding	73
19	DLL scoreboard coding and test case passing	47
20	DLL TB coverage report generation	23
21	DLL TB sequence development	62
22	DLL features to implement in TB	21
23	DLL compile clean up	45
24	DLL simulation bring up	55
25	DLL VC0 flow control bring up	120
26	DLL flow control test case bring up	66

Curriculum

1 : PCIe DLL basics

Introduction

Protocol overview

Features

Scenarios

Verification plan

2 : PCIe DLL UVC

Data link layer RTL coding

DLL Testbench architecture, testplan development

UVC architecture and components

UVC component coding

AXI UVC, DLL-TL and DLL-PL UVC

Testbench component integration

UVC sequence coding for AXI and DLL interface

Testcase coding

Testcase run and waveform analysis

Testbench integration

Simulations and waveform analysis

Functional coverage analysis

Benefits of eLearning?

Access to the Instructor - Ask questions to the Instructor who taught the course
Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

Course Instructor

Dedicated Trainer Accessible On Phone / Email / Whatsapp
Trainer Exp: 15 Years

Price - ₹7500 + GST

₹10,000 (25% Off)

10 hours left to avail at this price

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Course Highlights

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Vinutha M B

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10.04.2018

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