PCIe Physical Layer UVC Development Training

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PCIe Physical Layer UVC Development Training

About Course

PCIe Physical layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and PL-PHY interface.

These UVC are integrated with Physical Layer RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding.

Sessions also focused on developing the sequences for AXI, TL-DLL and PL-PHY interfaces, using these sequences to create the testcases.

Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.

Demo Videos
Unit NumberTopicDuration (Mins)
1PL TB Physical layer overview, PL interface, RTL and TB template coding74
2PL test bench template coding49
3PL LTSSM Detect to Polling.35
4PL Generate TS1 for Polling transitions24
5Polling.Active TS1 transmit65
6Polling.Active TS1 TS2 handshake till Configuration state46
7Link training update from Single lane to multi lane link29
8Configuration.LinkWidth.Start to accept State57
9CONFIG.LINKWIDTH_ACCEPT to CONFIG.LANENUM_ACCEPT60
10CONFIG.LANENUM_ACCEPT to L0102
11DLL Agent FC_INIT Sequence coding55
12PL DLL transmit path specific State machine coding59
13DLLP framing and transmit on DLL-PL interface38
14DLLP transmit per lane54
15DLLP transmit issue fix36
16PIPE UVC receiving DLLPs30
17FC DLLP driven by PIPE UVC in response to Design DLLPs60
18PL Design collecting DLLP properly58
19DLL RX UVC Collecting DLLPs64
20DLL TX UVC Generating TLPs72
21PL DUT Collecting TLPs, framing and sending to PIPE UVC62
22PIPE UVC Collecting TLPs and analyzing TLP header fields63
23PIPE UVC transmitting CplD TLP and DUT Collecting59
24DLL UVC collecting CplD TLP from PL DUT53
25PL DUT going to Recovery51
26Recovery sub state transitions and then to L045
27DLL Transmit interface monitor coding43
28DLL RX monitor, PIPE TX interface monitor and coverage coding96
29Scoreboard coding22
30Scoreboard mismatch debug97

 

Curriculum

Introduction
Protocol overview
Features
Scenarios
Verification plan
Physical layer RTL coding
Physical layer Testbench architecture, testplan development
UVC architecture and components
UVC component coding
AXI UVC, DLL-TL and PL-PHY UVC
Testbench component integration
UVC sequence coding for AXI, TL and PHY interface
Testcase coding
Testcase run and waveform analysis
Testbench integration
Simulations and waveform analysis
Functional coverage analysis

Benefits of eLearning?

 

  • Access to the Instructor - Ask questions to the Instructor who taught the course
  • Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Dedicated Trainer Accessible On Phone / Email / Whatsapp
  • Trainer Exp: 15 Years

Price - ₹7,500 + GST

₹10,000    (25% Off)

10 hours left to avail at this price

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