PCIe Data link Layer UVC Development Training

About Course

PCIe Data link layer UVC development is focused on developing UVC components for PCIe AXI, DLL-PL and DLL-TL interface. These UVC are integrated with DLL RTL code to develop the complete testbench. Course also focus on basics of transaction layer RTL coding, testbench architecture development, testplan and testcase coding. Sessions also focused on developing the sequences for AXI, TL-DLL and DLL-PL interfaces, using these sequences to create the testcases. Course also provides exposure to testcase debug concepts. However please note, code may not be in complete match with industry standard UVC code.


Protocol overview
Verification plan
Data link layer RTL coding
DLL Testbench architecture, testplan development
UVC architecture and components
UVC component coding
Testbench component integration
UVC sequence coding for AXI and DLL interface
Testcase coding
Testcase run and waveform analysis
Testbench integration
Simulations and waveform analysis
Functional coverage analysis

Course videos

Unit 1 PCIe DLL SES1 01:02:34
Unit 2 PCIe DLL SES2 01:45:52
Unit 3 PCIe DLL SES3 01:40:49
Unit 4 PCIe DLL SES4 01:58:39
Unit 5 PCIe DLL SES5 01:06:29

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