Functional Verification for experienced engineers

About Course

VLSI Front end course for Experienced Engineers (VG-FEDV) course is a 19 weeks course structured to enable experienced engineers gain expertise in functional verification. Majority cases, engineers does not get the hands on exposure to SV & UVM based testbench development, most of times goes in testcase coding and debug, leaving with very minimal SV & UVM expertise. This course is targeted for such engineers, to enable them get hands on exposure to complete Testbench development using SV & UVM.

Course includes more than 40+ assignments covering various aspects of Systemverilog, AXI Protocol, AXI VIP Development, Memory Controller verification, UVM constructs, AHB Protocol, AHB UVC Development and AHB Interconnect functional verification. All the aspects of the course are covered using practical examples. Systemverilog course involves more than 250+ examples covering all the aspects of Systemverilog. UVM training involves more than 100+ examples. All the examples and projects are developed from scratch as part of course sessions.


Classes : Object Oriented Programming
Arrays, Data Types, Literals, Operators
Scheduling Semantics, Inter process Synchronization
Processes, Threads, Tasks and Functions
Randomisation, Constraints
Interface, Clocking blocks, Program Block
Functional Coverage
Assertion Based Verification
System Tasks & Functions
Compiler Directives
AXI4.0 : Features, Signals, Timing Diagrams
AXI VIP Architecture Development
VIP Component Coding
AXI Slave model test case development
Test Case debugging
SoC Verification Concepts
Module Level Verification
Constrained Random Verification
Coverage Driven Verification
Directed Verification
Assertion Based Verification
Specification analysis
Verification Plan creation
Feature & Scenario Listing down
TB architecture creation
Building Top level verification environment
TB component coding and integration
Sanity test case and environment bring up
Complete test case coding
Building regression test suite
Functional coverage and code coverage analysis
What is UVM?
Need for Methodology?
UVM Overview
OOPs Basics
UVM TB Architecture
UVM Base classes
Simple UVM Test Example
UVM Command line processor
Reporting classes
Config DB, Resource DB
TLM 1.0
Sequence, Sequencer
Monitor and Scoreboard Basics
Virtual Sequencer
AHB Protocol
AHB UVC Development
Monitor and Scoreboard
Sequence library
Synchronization classes
Event, Barrier
Policy classes
Printer, comparator
Packer, Recorder
Phase jumping
Register Layer classes
Report catcher
Register Layer development for USB2.0 core
AHB Interconnect model functional verification
40+ detailed assignments covering all aspects of SV & UVM.

Course videos

Lecture 1 Functional verification overview Course pre-requisites, Assignment overview SV Language basic data types: Integer, Array, Dynamic array, Queue Working with arrays, Queues, mailbox Basic overview of task, function. 4:03:02
Lecture 2 SOC Design & Verification Overview, SV Language features, SV Basic Concepts, Testbench simulation detailed steps, SV Data types (static & dynamic), Mailbox for testbench connections 2:33:00
Lecture 3 Class, Randomization, Constraint, About Integer based data types, Mail Box Example, Memory handle(Object handle), Function and Task Examples, Drawbacks of Verilog based Verification 2:27:27
Lecture 4 SV Advantages, SV Language Features, Handshaking Signals Overview, Encapsulation, Inheritance, Polymorphism , Properties Declaration(2-state, 4-state, local, public, protected, signed, unsigned, rand, randc), Static, Automatic. 3:08:33
Lecture 5 Various types of copy(copy by handle, shallow copy, deep copy, $cast) How to Implement a Function, User Defined methods (Copy, Print, Compare, Pack, Unpack) 3:02:03
Lecture 6 Function new variations, Generator-BFM Examples(Different Ways of Connection using Mailbox). 1:56:25
Lecture 7 Pre_Randomize, Post_Randomize, Inline Constraints, Soft Constraints, Enum Data type, Extern Keyword. 2:21:02
Lecture 8 Static Casting, Encapsulation, Inheritance and Polymorphism Examples, vsim arguments types, Super and This Keywords 2:18:30
Lecture 9 Multiple Levels of Inheritance, Super &This Examples, Abstract Class, Use Case of Polymorphism of USB2.0, Parameterized Classes, Stack Example for Parameterized Class. 2:25:33
Lecture 10 Parameterized Class Importance in UVM, typedef, Static Methods & Properties, Interface Class, Interface Class Benefits and Examples, Constants, Scope Resolution Operator, Nested Class, Variable Scope & Global Scope, Copy by handle, Shallow Copy, Deep Copy Examples, $cast. 4:15:46
Lecture 11 $cast Example, Literals, Array Literals, Multi dimensional array Literals, Literals Importance, Operators-practical usage, Assignment Operators, Comparision Operators. 2:16:26
Lecture 12 Operators, Wild Equality Operators, Unary Reduction Operators, Streaming Operator, Operator Overloading, Operator Precedence. 2:23:20
Lecture 13 Array Classifications, Packed Array, Unpacked Array, Dynamic Array, Associative Array, Queue, Multi Dimensional Array. 3:16:01
Lecture 14 Queue Methods, Populating Queues, Queue Comparison, Data Types in SV, Integer based data types, their practical use cases, Event and Chandle data types 2:56:52
Lecture 15 User Defined Data Types, typedef, enum, Struct, Union, Array of Queues. 1:58:45
Lecture 16 Labelling, Inter Process Communication(Semaphore, Event, Mailbox), Setting up testbench for memory Verification. 2:47:34
Lecture 17 Memory test bench with configurable number of agents, Clocking Block, Mod port, Assertions in Interface. Implementing these in memory testbench. 3:55:39
Lecture 18 Fork, Join, Join_any, Join_none, System Task & Functions 3:14:23
Lecture 19 Program Block, Constraint Random Verification, Simple Constraints, Distribution Constraints, Implication Constraints, If-Else Constraints, Iterative Constraints, Ordering Constraints, Soft Constraints, Unique Constraint, Chip Select Constraints. 3:32:12
Lecture 20 Functional Coverage, Need of Functional Coverage, Functional Coverage Implementation, Functional Coverage Types, Functional Coverage Report Analysis, Code Coverage, Code Coverage Report Generation. 3:52:11
Lecture 21 Code Coverage Analysis, Code Coverage Types, UCDB, Code Coverage Example, Assertions 3:54:57
Lecture 22 Assertion Examples, DPI, Configuration Libraries, packages, Compiler Directives. 3:02:43
Lecture 23 Common array methods, atoi, Callback detailed explanation 2:27:51
Lecture 24 DMA Controller Session1 : DMA Controller specification reading, understanding architecture, design features, registers 03:07:36
Lecture 25 DMA Controller Session2: Feature listing down, test plan creation, testbench architecture, testbench component coding 02:33:41
Lecture 26 DMA Controller Session3: Testbench component coding, testbench integration, register model development 02:53:07
Lecture 27 DMA Controller Session4: Sanity test case bringup, reference model, checker and scoreboard implementation 03:19:14
Lecture 28 DMA Controller Session5: Functional test case coding, debug, update testbench components 02:18:45
Lecture 29 DMA Controller Session6: Functional test case coding 03:02:05
Lecture 30 DMA Controller Session7: Setting up regression, generate regression report, coverage report 03:10:20
Lecture 31 DMA Controller Session8: Analyze coverage report, create new tests, debug newly added tests 01:44:23
Lecture 32 DMA Controller Session9: Coverage analysis, adding new tests for coverage closure 01:44:23
Lecture 33 AXI4 Session1 : AXI protocol, AXI features, timing diagrams 03:31:12
Lecture 34 AXI Session2 : AXI features, signal descriptions, AXI VIP introduction 04:07:06
Lecture 35 AXI Session3 : AXI VIP architecture, VIP component coding, integration 01:49:21
Lecture 36 AXI Session4: AXI test case coding, validating AXI master VIP using slave VIP 24:55
Lecture 37 AXI Session5 : Coverage analysis and debug 01:08:08
UVM Lectures
Lecture 38 UVM Overview, Assignment Overview, Course Material Overview, Need for Methodology, AHB Interconnect Overview & Analogous Example, Importance of UVM Base Classes, UVM Based TB Architecture for AHB Interconnect, Differences between SV Based TB & UVM Based TB, Important Aspects of UVM, Factory With Analogous Example, UVM Factory, UVM TB Example, Function new() Importance in UVM with Analogy, UVM Root Detailed Explanation, OOPS Basics, Reproting Classes, Component Phasing & Common Phases, Objection. 03:32:41
Lecture 39 UVM Component, UVM Object, UVM Command Line Processor and Arguments, Importance of super & new in UVM, Objections, UVM TB Example, Guidelines for Coding UVM Components, Important Things about TB Phases Detailed Explanation, Required Phases for ahb_env, ahb_test, ahb_driver, ahb_monitor & ahb_sequencer, AHB Template Environment, Run_test, Factory, Registration. 03:46:30
Lecture 40 Reporting Classes, Factory Registration Detailed Explanation, Message Verbosity, Scheduled UVM Phases, Factory Concept with Analogy, 02:47:57
Lecture 41 "Reporting Classes, uvm_report_object different methods, Message Verbosity, Reference Verbosity, uvm_action, Scheduled UVM Phases, Factory, Active agent& Passive agent difference, Factory Usecases, Factory Methods, Print, Set Override Methods, uvm_config_db" 03:54:44
Lecture 42 "uvm_config_db use cases, uvm_config_db_methods, Uvm_config_db, uvm_resource_db, How uvm_config_db and uvm_resource_db are related, Benefits of uvm_config_db, TLM1.0(Ports, Connections, Push, Pull, FIFO, Broadcast) with Analogy, Types of Ports." 03:54:25
Lecture 43 Importance of uvm_do, PUSH Model, PULL Model, Connections, Drawback of PUSH/PULL Models, Analysis Model with Digital TV Subscription Analogy, Producer, Subscriber, TLM Example, Test Library, Sequence and Sequence Library, Mapping Testcase to Sequence, default_sequence , start sequence,raise/drop objections, Virtual sequence, Virtual Seuencer. 4:14:16
Lecture 44 Protocol Basics, ARM Processor types, Detailed Explanation of AHB Protocol, Role of Arbiter, Arbitration Phase, AHB Example, AHB Signals& their decoding, Handshaking Signals Overview, Priority Arbitration, Round Robin Arbitration, Arbitration Phase All Signals, Address Phase, Data Phase, Basic Transfer Explanation with the clk edge, Wait state, Analysing the timing diagram& its Importance for Verification Engineer, Pipelining Detailed Explanation, Signal Phases, AHB Transaction Example, Little endian architecture, Big endian architecture, Hprot, Hresp(OKAY,ERROR,RETRY,SPLIT), Htrans Possibilities, AHB features, Aligned& Unaligned transfer, transfer, Burst Transfers , Differences between incrementing and wrapping transfers, Wrapping Detailed Explanation& Calculations. 3:35:27
Lecture 45 AHB Master , Slave Signals, Signal Decoding in AHB(SEQ, NON-SEQ, BUSY, IDLE,INCR,WRAP), Hprot signal Explanation with Analogy, Bufferable, Cacheble, Okay Response,Error Response,SPLIT or RETRY, Two Cycle Response, AHB Arbitration, Exclusive Transfers, AHB UVC Development, AHB UVC Template Coding, AHB UVC Functinality Coding. 3:43:34
Lecture 46 Early burst termination, AHB UVC Functional Coding, ahb_tx coding(fields, methods, constraints), resp, exokay are non rand, why?, Implementing wrap test, How to get rid of unknown 'x' values in waveform after simulation, Driver coding(drive_tx, arb_phase, addr_phase, data_phase), responder, monitor, coverage, UVM Preparation focus areas, Finding the issues with AHB UVC. 3:50:56
Lecture 47 Fixing the Debug issues in AHB UVC, Developing more tests(Checking different burst types, Checking different port, Checking exclusive access, checking write/reads), Setting UVC parameters in ahb_uvc_config file, Resolving new issues, Implementing test with multiple write/reads, Implementing final AHB UVC without any debugging issues. ,AHB UVC, Master UVC, Slave UVC, AHB Protocol Interview Questions & Explanation. 4:10:55
Lecture 48 AHB Interconnect, Testbench development, Sequence library, Defining library, Adding Sequences into Library, Creating tests using Library, Benefit of Library, Important things of Sequence Library. 4:36:32
Lecture 49 AHB Interconnect features& Implementing Testcases, Scoreboard, Virtual Sequencer& Virtual Sequences, APB agent coding 4:06:44
Lecture 50 "Overview of TB & Design Fuctionality with DMA Controller Analogy, Design Verification Scenario Requirements for Various possible Designs, Layering of sequences, Importance of Sequence Layering, UVM Scheduled Phases, Default Sequence, Difference between default_sequence & start default_sequence, Debug options available in UVM." 3:49:04
Lecture 51 Callbacks, TLM2.0, blocking & non-blocking , Concept of Delay, uvm_event, Updating Event Callbacks in existing TB, event, uvm_barrier, uvm_barrier_pool, uvm_callbacks, UVM base classes for callback implementation, Usecases of Callbacks. 4:03:28
Lecture 52 uvm_heartbeat, heartbeat window, Steps to implement uvm_heartbeat in TB, UVM Reporting Classes, uvm_report_catcher 1:31:28
Lecture 53 "Phase Jumping, Implementation of Phase Jumping, UVM_domain, Policy Classes, Printer, Comparer, Packer, Recorder." 2:13:28
Lecture 54 "Register Layer Classes Detailed Explanation, RAL Model Development, RAL Base Classes & Hierarchy, Steps in coding Register Definition, Types of Access of UVM Register Model, Need of Functional Coverage in Register Model, Register front door access, Register back door access, Integration of register model in TB, Use cases of Register Model, Sequencer and Sequence Methods" 2:54:28
Lecture 55 "Developing Register Model, Register Block Instantiation, Register File Instantiation, Mapping all the Registers in to Register map, Developing testcases & TB Components using Reg Model, Different Methods of Register Model Base Classes, SPI Controller testbench Detailed Explanation" 1:50:28
Lecture 56 Register model testcases, Ral testcase debug 1:01:28
Lecture 57 UVM TLM Push & Pull based testbench example 1:05:28

Benefits of eLearning:

  • - Access to the Instructor - Ask questions to the Instructor who taught the course
  • - Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

continue to register

Have an account ? Login Fast

Login to Continue

If you face any Issue Contact Administrator.