Functional Verification training for freshers

About Course

VLSI Front end course for freshers (VG-FEDV) is 6 months course structured to enable BTech/BE and MTech/ME freshers gain in depth exposure to all the aspects of VLSI front end Design and verification. VLSI front end course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, Systemverilog, UVM, Linux, revision management and scripting. Course also includes training on soft skill for effective interview performance.

Lack of fundamentals in advanced digital design, analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI Front end training course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. Course is completely practical oriented with each aspect of course involving multiple hands on projects. All the courses are offered by trainers with 10+ years of relevant experience. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, RTL coding, Verilog, System verilog, RTL debug, UNIX, and scripting.

... VLSI Design flow(ASIC flow) course covers complete ASIC flow exposure from specifications till GDSII including Architecture, Specifications, RTL coding, lint checks, RTL integration, connectivity checks, functional verification, synthesis, Gate level simulations, formal equivalence checks, STA, placement and routing, clock tree synthesis, DFT, custom layout and post silicon validation. SOC Design and verification focus on SOC design concepts, SOC architecture, SOC verification concepts and differences when compared to module level verification.
Advanced Digital Design course focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronizers, timing violation fixing, etc.
Verilog and RTL coding course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.
Systemverilog course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.
RTL debug course will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
Linux OS course ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.
Scripting course will focus PERL essential concepts. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage in industry.
Soft skill training will prepare student on how to face interviews effectively, right body language, etc.
Course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.
Students planning to pursue complex projects after this course can do by paying a nominal fee. Institute offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.


RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
Custom layout
Post silicon validation
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Refer to Advanced digital design training page for detailed course contents
SoC Verification Concepts
Module Level Verification
Constrained Random Verification
Coverage Driven Verification
Directed Verification
Assertion Based Verification
Verilog language constructs
Verilog design coding examples covering more than 20 standard designs
Classes : Object Oriented Programming
Arrays, Data Types, Literals, Operators
Scheduling Semantics, Inter process Synchronization
Processes, Threads, Tasks and Functions
Randomization, Constraints
Interface, Clocking blocks, Program Block
Functional Coverage
Assertion Based Verification
System Tasks & Functions
Compiler Directives
AXI Protocol Concepts : Features, Signals, Timing Diagrams
AXI VIP Architecture Development
VIP Component Coding
AXI Slave model test case development
Test Case debugging
Schematic tracing
RTL tracing
FIxing RTL and TB syntax and logical errors
Reading design specification
Understanding design architecture, sub blocks, register definitions, interfaces
Listing down features, scenarios
Develop testplan
Functional coverage point list down
Develop Testbench architecture
Testbench component coding and integration
Skeletal TB structure coding
Functional coding
Develop sanity testcases(smoke testcases)
Bringup testbench environment using sanity testcases
Develop rest of testbench components
Develop functional testcases
Setup regression using Python script
Verification closure
Debug regression failures
Functional, Code and assertion coverage analysis
How UVM evolved?
UVM Testbench Architecture
UVM Base classes
UVM Macros
UVM Messaging
UVM simulation phases
TLM 1.0
Config db, Resource db, Factory
Sequences, Sequence Library
Virtual Sequences and virtual sequencers
Developing scoreboard in UVM
Developing testcases in UVM
Command line processor
UVC development for APB protocol
UVC development for AHB protocol
Developing configurable UVC's
SOC Architecture overview
SOC design concepts
SOC verification concepts
SOC Components
SOC use cases
SOC Testbench architecture
SOC Test Case coding
SOC verification differences with module verification
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
PERL Interpreter
File management
Regular expressions
Object oriented PERL
PERL modules
Facing interviews effectively
industry work culture
Group discussions
100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting

Course videos

Lecture 1 VLSI Design flow Session1 02:52:37
Lecture 2 VLSI Design flow Session2 02:01:39
Lecture 3 Digital Session1 03:18:36
Lecture 4 Digital Session2 03:11:05
Lecture 5 Digital Session3 02:55:05
Lecture 6 Digital Session4 03:07:10
Lecture 7 Digital Session5 02:55:39
Lecture 8 Digital Session6 02:42:33
Lecture 9 Digital Session7 03:35:13
Lecture 10 Digital Session8 01:53:34
Lecture 11 Linux Session1 01:10:00
Lecture 12 Linux Session2 01:51:39
Lecture 13 Linux Session3 02:22:40
Lecture 14 Linux Session4 02:11:10
Lecture 15 Linux Session5 01:33:52
Lecture 16 Linux Session6 01:34:18
Lecture 17 PERL Session1 02:26:37
Lecture 18 PERL Session2 02:37:48
Lecture 19 PERL Session3 02:51:34
Lecture 20 PERL Session4 02:51:00
Lecture 21 PERL Session5 02:10:00
Lecture 22 PERL Session6 03:18:50
Lecture 23 Verilog Session1 03:00:13
Lecture 24 Verilog Session2 03:17:19
Lecture 25 Verilog session3 04:18:16
Lecture 26 Verilog Session4 03:32:52
Lecture 27 Verilog Session5 03:37:52
Lecture 28 Verilog Session6 03:35:25
Lecture 29 Verilog Session7 04:35:08
Lecture 30 Verilog Session8 04:39:25
Lecture 31 Verilog Session9 03:19:25
Lecture 32 Verilog Session10 04:02:39
Lecture 33 Verilog Session11 03:22:14
Lecture 34 Verilog Session12 02:46:52
Lecture 35 Verilog Session13 01:30:00
Lecture 36 Verilog Session14 00:25:30
Lecture 37 Verilog Session15 02:03:00
Lecture 38 SV Session1 3:00:13
Lecture 39 SV Session2 3:17:19
Lecture 40 SV Session3 4:18:16
Lecture 41 SV Session4 3:33:52
Lecture 42 SV Session5 3:37:52
Lecture 43 SV Session6 3:35:25
Lecture 44 SV Session7 4:35:08
Lecture 45 SV Session8 4:39:25
Lecture 46 SV Session9 3:19:25
Lecture 47 SV Session10 4:02:39
Lecture 48 SV Session11 3:02:30
Lecture 49 SV Session12 3:15:39
Lecture 50 AXI3.0 Protocol 3:22:14
Lecture 51 AXI VIP Development 2:46:53
Lecture 52 AXI VIP Development 1:27:46
Lecture 53 AXI VIP Development 1:30:00
Lecture 54 AXI VIP Development 24:55
Lecture 55 AXI VIP Development 01:08:08
Lecture 56 DMA Controller Functional Verification Session 1 03:07:36
Lecture 57 DMA Controller Functional Verification Session 2 02:31:41
Lecture 58 DMA Controller Functional Verification Session 3 02:53:07
Lecture 59 DMA Controller Functional Verification Session 4 03:19:14
Lecture 60 DMA Controller Functional Verification Session 5 02:18:45
Lecture 61 DMA Controller Functional Verification Session 6 03:02:05
Lecture 62 DMA Controller Functional Verification Session 7 03:10:20
Lecture 63 DMA Controller Functional Verification Session 8 01:44:23
Lecture 64 DMA Controller Functional Verification Session 8 2:44:23
Lecture 65 DMA Controller Functional Verification Session 8 01:44:23
Lecture 66 DMA Controller Functional Verification Session 8 01:44:23
Lecture 67 DMA Controller Functional Verification Session 8 01:44:23
Lecture 68 UVM Session1 03:32:41
Lecture 69 UVM Session2 03:46:15
Lecture 70 UVM Session3 02:47:01
Lecture 71 UVM Session4 03:55:00
Lecture 72 UVM Session5 : AHB5 Protocol training 03:54:01
Lecture 73 UVM Session6 : AHB5 Protocol training and UVC Development 04:14:49
Lecture 74 UVM Session7 : AHB UVC Development 03:35:09
Lecture 75 UVM Session8 : AHB UVC Development 03:43:08
Lecture 76 SOC Design and verification 03:09:23
Lecture 77 Revision Management 02:00:00

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