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| AHB Interconnect model used as a reference design to learn all the aspects of complex UVM based Testbench setup |
| AHB Interconnect will be verified from scratch while teaching all aspects of UVM |
| UVM/OVM TB Architecture |
| UVM Root |
| UVM Class Library, Macros, Utilities |
| UVM Factory |
| Config_db, Resource_db |
| Command line processor |
| Synchronization classes |
| uvm_barrier |
| uvm_event |
| Container classes |
| Policy classes |
| uvm_printer |
| uvm_recorder |
| uvm_packer |
| uvm_comparer |
| UVM Components, Comparators |
| Sequences, Sequencers |
| Sequence library |
| virtual sequencer and sequences |
| Stimulus Modelling, Sequences & Sequencers |
| Creating UVCs and Environment |
| Simulation Phases |
| Scheduled phases |
| TLM1.0 |
| Push |
| Pull |
| FIFO |
| Analysis |
| TLM2.0 |
| Blocking transport |
| Non-blocking transport |
| Configuring TB Environment |
| Objections |
| Register Layer, Configuration DB & Resource DB |
| Connecting multiple UVCs |
| Creating TB infrastructure |
| uvm_heartbeat |
| uvm_report_catcher |
| Phase jumping |
| uvm_domain |
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| AHB Protocol |
| AHB System architecture |
| Features |
| Signals |
| Timing Diagrams |
| AHB UVC Architecture |
| AHB UVC Component Coding |
| AHB UVC Sequence & Test Development |
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| AHB Interconnect Testbench Architecture |
| AHB UVC & APB UVC in Interconnect Testbench setup |
| VIP Component Coding |
| Verification Component Coding |
| Testcase & virtual sequence Development & Debug |
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| Listing down registers |
| Creating Register Model |
| Integrating Register Model in to Testbench |
| Using Register Model to create tests |
| Using Register Model in scoreboard |
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| UVC Development for AXI Protocol |
| PCIe LTSSM FSM Verification |
| Register Model Development for SPI Core |
Course videos
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| Lecture 1 | UVM Overview, Assignment Overview, Course Material Overview, Need for Methodology, AHB Interconnect Overview & Analogous Example, Importance of UVM Base Classes, UVM Based TB Architecture for AHB Interconnect, Differences between SV Based TB & UVM Based TB, Important Aspects of UVM, Factory With Analogous Example, UVM Factory, UVM TB Example, Function new() Importance in UVM with Analogy, UVM Root Detailed Explanation, OOPS Basics, Reproting Classes, Component Phasing & Common Phases, Objection. | 03:32:41 | |
| Lecture 2 | UVM Component, UVM Object, UVM Command Line Processor and Arguments, Importance of super & new in UVM, Objections, UVM TB Example, Guidelines for Coding UVM Components, Important Things about TB Phases Detailed Explanation, Required Phases for ahb_env, ahb_test, ahb_driver, ahb_monitor & ahb_sequencer, AHB Template Environment, Run_test, Factory, Registration. | 03:46:30 | |
| Lecture 3 | Reporting Classes, Factory Registration Detailed Explanation, Message Verbosity, Scheduled UVM Phases, Factory Concept with Analogy, | 02:47:57 | |
| Lecture 4 | "Reporting Classes, uvm_report_object different methods, Message Verbosity, Reference Verbosity, uvm_action, Scheduled UVM Phases, Factory, Active agent& Passive agent difference, Factory Usecases, Factory Methods, Print, Set Override Methods, uvm_config_db" | 03:54:44 | |
| Lecture 5 | "uvm_config_db use cases, uvm_config_db_methods, Uvm_config_db, uvm_resource_db, How uvm_config_db and uvm_resource_db are related, Benefits of uvm_config_db, TLM1.0(Ports, Connections, Push, Pull, FIFO, Broadcast) with Analogy, Types of Ports." | 03:54:25 | |
| Lecture 6 | Importance of uvm_do, PUSH Model, PULL Model, Connections, Drawback of PUSH/PULL Models, Analysis Model with Digital TV Subscription Analogy, Producer, Subscriber, TLM Example, Test Library, Sequence and Sequence Library, Mapping Testcase to Sequence, default_sequence , start sequence,raise/drop objections, Virtual sequence, Virtual Seuencer. | 4:14:16 | |
| Lecture 7 | Protocol Basics, ARM Processor types, Detailed Explanation of AHB Protocol, Role of Arbiter, Arbitration Phase, AHB Example, AHB Signals& their decoding, Handshaking Signals Overview, Priority Arbitration, Round Robin Arbitration, Arbitration Phase All Signals, Address Phase, Data Phase, Basic Transfer Explanation with the clk edge, Wait state, Analysing the timing diagram& its Importance for Verification Engineer, Pipelining Detailed Explanation, Signal Phases, AHB Transaction Example, Little endian architecture, Big endian architecture, Hprot, Hresp(OKAY,ERROR,RETRY,SPLIT), Htrans Possibilities, AHB features, Aligned& Unaligned transfer, transfer, Burst Transfers , Differences between incrementing and wrapping transfers, Wrapping Detailed Explanation& Calculations. | 3:35:27 | |
| Lecture 8 | AHB Master , Slave Signals, Signal Decoding in AHB(SEQ, NON-SEQ, BUSY, IDLE,INCR,WRAP), Hprot signal Explanation with Analogy, Bufferable, Cacheble, Okay Response,Error Response,SPLIT or RETRY, Two Cycle Response, AHB Arbitration, Exclusive Transfers, AHB UVC Development, AHB UVC Template Coding, AHB UVC Functinality Coding. | 3:43:34 | |
| Lecture 9 | Early burst termination, AHB UVC Functional Coding, ahb_tx coding(fields, methods, constraints), resp, exokay are non rand, why?, Implementing wrap test, How to get rid of unknown 'x' values in waveform after simulation, Driver coding(drive_tx, arb_phase, addr_phase, data_phase), responder, monitor, coverage, UVM Preparation focus areas, Finding the issues with AHB UVC. | 3:50:56 | |
| Lecture 10 | Fixing the Debug issues in AHB UVC, Developing more tests(Checking different burst types, Checking different port, Checking exclusive access, checking write/reads), Setting UVC parameters in ahb_uvc_config file, Resolving new issues, Implementing test with multiple write/reads, Implementing final AHB UVC without any debugging issues. ,AHB UVC, Master UVC, Slave UVC, AHB Protocol Interview Questions & Explanation. | 4:10:55 | |
| Lecture 11 | AHB Interconnect, Testbench development, Sequence library, Defining library, Adding Sequences into Library, Creating tests using Library, Benefit of Library, Important things of Sequence Library. | 4:36:32 | |
| Lecture 12 | AHB Interconnect features& Implementing Testcases, Scoreboard, Virtual Sequencer& Virtual Sequences, APB agent coding | 4:06:44 | |
| Lecture 13 | "Overview of TB & Design Fuctionality with DMA Controller Analogy, Design Verification Scenario Requirements for Various possible Designs, Layering of sequences, Importance of Sequence Layering, UVM Scheduled Phases, Default Sequence, Difference between default_sequence & start default_sequence, Debug options available in UVM." | 3:49:04 | |
| Lecture 14 | Callbacks, TLM2.0, blocking & non-blocking , Concept of Delay, uvm_event, Updating Event Callbacks in existing TB, event, uvm_barrier, uvm_barrier_pool, uvm_callbacks, UVM base classes for callback implementation, Usecases of Callbacks. | 4:03:28 | |
| Lecture 15 | uvm_heartbeat, heartbeat window, Steps to implement uvm_heartbeat in TB, UVM Reporting Classes, uvm_report_catcher | 1:31:28 | |
| Lecture 16 | "Phase Jumping, Implementation of Phase Jumping, UVM_domain, Policy Classes, Printer, Comparer, Packer, Recorder." | 2:13:28 | |
| Lecture 17 | "Register Layer Classes Detailed Explanation, RAL Model Development, RAL Base Classes & Hierarchy, Steps in coding Register Definition, Types of Access of UVM Register Model, Need of Functional Coverage in Register Model, Register front door access, Register back door access, Integration of register model in TB, Use cases of Register Model, Sequencer and Sequence Methods" | 2:54:28 | |
| Lecture 18 | "Developing Register Model, Register Block Instantiation, Register File Instantiation, Mapping all the Registers in to Register map, Developing testcases & TB Components using Reg Model, Different Methods of Register Model Base Classes, SPI Controller testbench Detailed Explanation" | 1:50:28 | |
| Lecture 19 | Register model testcases, Ral testcase debug | 1:01:28 | |
| Lecture 20 | UVM TLM Push & Pull based testbench example | 1:05:28 |
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