UVM Advanced training with 2 hands on projects

About Course

UVM for Functional Verification elearning course (VG-UVM) is a 68 hours theory, 40 hours labs course offered by Sreenivasa Reddy, Founder, VLSIGuru. Course is structured to enable engineers develop skills in full breadth of UVM features in complex testbench development. UVM course is targeted for functional verification engineers with Systemverilog expertise and looking to explore advanced methodology concepts like factory, databases and register layer. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.

UVM course is divided in to 3 aspects, initally lectures focused on in depth understanding of language constructs using detailed examples, second part of lectures focused on AHB and APB protocols, UVC development for these protocols and last set of lectures focused AHB interconnect verification with all the verification starting from specification reading till functional verification closure using regression. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.

... UVM constructs are learnt using more than 100+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc. AHB Interconnect design is used as a reference example to learn all above aspects of UVM. These examples cover more than 90% of questions asked in VLSI interviews.
UVM course also covers multiple hands-on verification projects based on AHB, APB, and AHB Interconnect. Learning starts from simple projects like AHB UVC development to complex design verification projects involving Functional verification of AHB Interconnect using SV & UVM. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.
UVM course has 15 detailed assignments. Student will be provided with 1-1 guidance in solving these assignments. Student is offered with multiple interview opportunities based on performance in assignments.
Below is salient features of UVM for Functional Verification training course.
UVM language constructs learning using 100+ detailed examples
UVC development for AHB and APB protocols
AHB Interconnect verification
20+ detailed assignments covering all aspects of UVM


AHB Interconnect model used as a reference design to learn all the aspects of complex UVM based Testbench setup
AHB Interconnect will be verified from scratch while teaching all aspects of UVM
UVM/OVM TB Architecture
UVM Root
UVM Class Library, Macros, Utilities
UVM Factory
Config_db, Resource_db
Command line processor
Synchronization classes
Container classes
Policy classes
UVM Components, Comparators
Sequences, Sequencers
Sequence library
virtual sequencer and sequences
Stimulus Modelling, Sequences & Sequencers
Creating UVCs and Environment
Simulation Phases
Scheduled phases
Blocking transport
Non-blocking transport
Configuring TB Environment
Register Layer, Configuration DB & Resource DB
Connecting multiple UVCs
Creating TB infrastructure
Phase jumping
AHB Protocol
AHB System architecture
Timing Diagrams
AHB UVC Architecture
AHB UVC Component Coding
AHB UVC Sequence & Test Development
AHB Interconnect Testbench Architecture
AHB UVC & APB UVC in Interconnect Testbench setup
VIP Component Coding
Verification Component Coding
Testcase & virtual sequence Development & Debug
Listing down registers
Creating Register Model
Integrating Register Model in to Testbench
Using Register Model to create tests
Using Register Model in scoreboard
UVC Development for AXI Protocol
PCIe LTSSM FSM Verification
Register Model Development for SPI Core

Course videos

Lecture 1 UVM Overview, Assignment Overview, Course Material Overview, Need for Methodology, AHB Interconnect Overview & Analogous Example, Importance of UVM Base Classes, UVM Based TB Architecture for AHB Interconnect, Differences between SV Based TB & UVM Based TB, Important Aspects of UVM, Factory With Analogous Example, UVM Factory, UVM TB Example, Function new() Importance in UVM with Analogy, UVM Root Detailed Explanation, OOPS Basics, Reproting Classes, Component Phasing & Common Phases, Objection. 03:32:41
Lecture 2 UVM Component, UVM Object, UVM Command Line Processor and Arguments, Importance of super & new in UVM, Objections, UVM TB Example, Guidelines for Coding UVM Components, Important Things about TB Phases Detailed Explanation, Required Phases for ahb_env, ahb_test, ahb_driver, ahb_monitor & ahb_sequencer, AHB Template Environment, Run_test, Factory, Registration. 03:46:30
Lecture 3 Reporting Classes, Factory Registration Detailed Explanation, Message Verbosity, Scheduled UVM Phases, Factory Concept with Analogy, 02:47:57
Lecture 4 "Reporting Classes, uvm_report_object different methods, Message Verbosity, Reference Verbosity, uvm_action, Scheduled UVM Phases, Factory, Active agent& Passive agent difference, Factory Usecases, Factory Methods, Print, Set Override Methods, uvm_config_db" 03:54:44
Lecture 5 "uvm_config_db use cases, uvm_config_db_methods, Uvm_config_db, uvm_resource_db, How uvm_config_db and uvm_resource_db are related, Benefits of uvm_config_db, TLM1.0(Ports, Connections, Push, Pull, FIFO, Broadcast) with Analogy, Types of Ports." 03:54:25
Lecture 6 Importance of uvm_do, PUSH Model, PULL Model, Connections, Drawback of PUSH/PULL Models, Analysis Model with Digital TV Subscription Analogy, Producer, Subscriber, TLM Example, Test Library, Sequence and Sequence Library, Mapping Testcase to Sequence, default_sequence , start sequence,raise/drop objections, Virtual sequence, Virtual Seuencer. 4:14:16
Lecture 7 Protocol Basics, ARM Processor types, Detailed Explanation of AHB Protocol, Role of Arbiter, Arbitration Phase, AHB Example, AHB Signals& their decoding, Handshaking Signals Overview, Priority Arbitration, Round Robin Arbitration, Arbitration Phase All Signals, Address Phase, Data Phase, Basic Transfer Explanation with the clk edge, Wait state, Analysing the timing diagram& its Importance for Verification Engineer, Pipelining Detailed Explanation, Signal Phases, AHB Transaction Example, Little endian architecture, Big endian architecture, Hprot, Hresp(OKAY,ERROR,RETRY,SPLIT), Htrans Possibilities, AHB features, Aligned& Unaligned transfer, transfer, Burst Transfers , Differences between incrementing and wrapping transfers, Wrapping Detailed Explanation& Calculations. 3:35:27
Lecture 8 AHB Master , Slave Signals, Signal Decoding in AHB(SEQ, NON-SEQ, BUSY, IDLE,INCR,WRAP), Hprot signal Explanation with Analogy, Bufferable, Cacheble, Okay Response,Error Response,SPLIT or RETRY, Two Cycle Response, AHB Arbitration, Exclusive Transfers, AHB UVC Development, AHB UVC Template Coding, AHB UVC Functinality Coding. 3:43:34
Lecture 9 Early burst termination, AHB UVC Functional Coding, ahb_tx coding(fields, methods, constraints), resp, exokay are non rand, why?, Implementing wrap test, How to get rid of unknown 'x' values in waveform after simulation, Driver coding(drive_tx, arb_phase, addr_phase, data_phase), responder, monitor, coverage, UVM Preparation focus areas, Finding the issues with AHB UVC. 3:50:56
Lecture 10 Fixing the Debug issues in AHB UVC, Developing more tests(Checking different burst types, Checking different port, Checking exclusive access, checking write/reads), Setting UVC parameters in ahb_uvc_config file, Resolving new issues, Implementing test with multiple write/reads, Implementing final AHB UVC without any debugging issues. ,AHB UVC, Master UVC, Slave UVC, AHB Protocol Interview Questions & Explanation. 4:10:55
Lecture 11 AHB Interconnect, Testbench development, Sequence library, Defining library, Adding Sequences into Library, Creating tests using Library, Benefit of Library, Important things of Sequence Library. 4:36:32
Lecture 12 AHB Interconnect features& Implementing Testcases, Scoreboard, Virtual Sequencer& Virtual Sequences, APB agent coding 4:06:44
Lecture 13 "Overview of TB & Design Fuctionality with DMA Controller Analogy, Design Verification Scenario Requirements for Various possible Designs, Layering of sequences, Importance of Sequence Layering, UVM Scheduled Phases, Default Sequence, Difference between default_sequence & start default_sequence, Debug options available in UVM." 3:49:04
Lecture 14 Callbacks, TLM2.0, blocking & non-blocking , Concept of Delay, uvm_event, Updating Event Callbacks in existing TB, event, uvm_barrier, uvm_barrier_pool, uvm_callbacks, UVM base classes for callback implementation, Usecases of Callbacks. 4:03:28
Lecture 15 uvm_heartbeat, heartbeat window, Steps to implement uvm_heartbeat in TB, UVM Reporting Classes, uvm_report_catcher 1:31:28
Lecture 16 "Phase Jumping, Implementation of Phase Jumping, UVM_domain, Policy Classes, Printer, Comparer, Packer, Recorder." 2:13:28
Lecture 17 "Register Layer Classes Detailed Explanation, RAL Model Development, RAL Base Classes & Hierarchy, Steps in coding Register Definition, Types of Access of UVM Register Model, Need of Functional Coverage in Register Model, Register front door access, Register back door access, Integration of register model in TB, Use cases of Register Model, Sequencer and Sequence Methods" 2:54:28
Lecture 18 "Developing Register Model, Register Block Instantiation, Register File Instantiation, Mapping all the Registers in to Register map, Developing testcases & TB Components using Reg Model, Different Methods of Register Model Base Classes, SPI Controller testbench Detailed Explanation" 1:50:28
Lecture 19 Register model testcases, Ral testcase debug 1:01:28
Lecture 20 UVM TLM Push & Pull based testbench example 1:05:28

Benefits of eLearning:

  • - Access to the Instructor - Ask questions to the Instructor who taught the course
  • - Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
  • - Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready

continue to register

Have an account ? Login Fast

Login to Continue

If you face any Issue Contact Administrator.