SystemVerilog for Functional Verification

About Course

System Verilog for Functional Verification training (VG-SV) course is a 120 hours theory, 80 hours labs course structured to enable engineers gain expertize in Systemverilog for functional verification including complex testbench development. System Verilog Training course is targeted towards engineers looking to explore advanced functional verification techniques involving constrained random verification, assertion based verification, and coverage based verification. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. System Verilog Training course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.

System Verilog Training course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AXI, APB), VIP development for these protocols and one industry standard project with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.

... System Verilog language in learnt using more than 200+ detailed examples covering all aspects of SV starting from data types, operators, OOPs(Classes), Arrays, Inter-process synchronization, Interface, Program, constraints and randomization, code coverage, functional coverage, DPI and assertions. These examples cover more than 90% of questions asked in VLSI interviews.

System Verilog Training course also covers multiple hands-on verification projects based on AXI, APB, Ethernet, and Memory controller. Learning starts from simple projects like Ethernet switch design verification to complex design verification projects involving Functional verification of Memory controller. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.

System Verilog Training course also involves 25+ detailed assignments (20+ assignments on SV language, 2 assignments on protocol, 2 on VIP development, 2 on industry standard projects). These assignments are prepared by industry experts covering all aspects of SV from language constructs, protocols and multiple industry standard projects. Student gets to work on these assignments with complete guidance from trainers and student learning is evaluated using completion of assignments as the sole criteria. Student is offered with multiple (more than 10+) interview opportunities based on performance in assignments.

Below is salient features of System Verilog Training in Functional Verification course.

SV Language construct learning using 200+ detailed examples
AXI Protocol & AXI VIP Development
APB protocol, APB VIP Development
Memory Controller Functional Verification
20+ detailed assignments covering all aspects of SV, AXI, APB, and Memory controller project.


Design elements
Overview of hierarchy
Compilation and elaboration
Name spaces
Simulation time units and precision
Classes : Object Oriented Programming
Arrays, Data Types, Literals, Operators
Scheduling Semantics, Inter process Synchronisation
Processes, Threads, Tasks and Functions
Randomisation, Constraints
Interface, Clocking blocks, Program Block
Functional Coverage
Assertion Based Verification
System Tasks & Functions
Compiler Directives
SoC Verification Concepts
Module Level Verification
Constrained Random Verification
Coverage Driven Verification
Directed Verification
Assertion Based Verification
AXI4.0 Protocol : Features, Signals, Timing Diagrams
AXI VIP Architecture
VIP Component Coding
AXI Slave model testcase coding
Testcase debugging
Specification analysis
Verification Plan creation
Feature & Scenario Listing down
TB architecture creation
Building Top level verification environment
TB component coding and integration
Sanity test case and environment bring up
Complete test case coding
Building regression test suite
Functional coverage and code coverage analysis
VIP Development for one of OCP/Wishbone/APB/Ethernet Protocols
Verification of PCIEx Physical Layer LTSSM FSM from scratch
Functional Verification of a complex module

Course videos

Lecture 1 Functional verification overview Course pre-requisites, Assignment overview SV Language basic data types: Integer, Array, Dynamic array, Queue Working with arrays, Queues, mailbox Basic overview of task, function. 4:03:02
Lecture 2 SOC Design & Verification Overview, SV Language features, SV Basic Concepts, Testbench simulation detailed steps, SV Data types (static & dynamic), Mailbox for testbench connections 2:33:00
Lecture 3 Class, Randomization, Constraint, About Integer based data types, Mail Box Example, Memory handle(Object handle), Function and Task Examples, Drawbacks of Verilog based Verification 2:27:27
Lecture 4 SV Advantages, SV Language Features, Handshaking Signals Overview, Encapsulation, Inheritance, Polymorphism , Properties Declaration(2-state, 4-state, local, public, protected, signed, unsigned, rand, randc), Static, Automatic. 3:08:33
Lecture 5 Various types of copy(copy by handle, shallow copy, deep copy, $cast) How to Implement a Function, User Defined methods (Copy, Print, Compare, Pack, Unpack) 3:02:03
Lecture 6 Function new variations, Generator-BFM Examples(Different Ways of Connection using Mailbox). 1:56:25
Lecture 7 Pre_Randomize, Post_Randomize, Inline Constraints, Soft Constraints, Enum Data type, Extern Keyword. 2:21:02
Lecture 8 Static Casting, Encapsulation, Inheritance and Polymorphism Examples, vsim arguments types, Super and This Keywords 2:18:30
Lecture 9 Multiple Levels of Inheritance, Super &This Examples, Abstract Class, Use Case of Polymorphism of USB2.0, Parameterized Classes, Stack Example for Parameterized Class. 2:25:33
Lecture 10 Parameterized Class Importance in UVM, typedef, Static Methods & Properties, Interface Class, Interface Class Benefits and Examples, Constants, Scope Resolution Operator, Nested Class, Variable Scope & Global Scope, Copy by handle, Shallow Copy, Deep Copy Examples, $cast. 4:15:46
Lecture 11 $cast Example, Literals, Array Literals, Multi dimensional array Literals, Literals Importance, Operators-practical usage, Assignment Operators, Comparision Operators. 2:16:26
Lecture 12 Operators, Wild Equality Operators, Unary Reduction Operators, Streaming Operator, Operator Overloading, Operator Precedence. 2:23:20
Lecture 13 Array Classifications, Packed Array, Unpacked Array, Dynamic Array, Associative Array, Queue, Multi Dimensional Array. 3:16:01
Lecture 14 Queue Methods, Populating Queues, Queue Comparison, Data Types in SV, Integer based data types, their practical use cases, Event and Chandle data types 2:56:52
Lecture 15 User Defined Data Types, typedef, enum, Struct, Union, Array of Queues. 1:58:45
Lecture 16 Labelling, Inter Process Communication(Semaphore, Event, Mailbox), Setting up testbench for memory Verification. 2:47:34
Lecture 17 Memory test bench with configurable number of agents, Clocking Block, Mod port, Assertions in Interface. Implementing these in memory testbench. 3:55:39
Lecture 18 Fork, Join, Join_any, Join_none, System Task & Functions 3:14:23
Lecture 19 Program Block, Constraint Random Verification, Simple Constraints, Distribution Constraints, Implication Constraints, If-Else Constraints, Iterative Constraints, Ordering Constraints, Soft Constraints, Unique Constraint, Chip Select Constraints. 3:32:12
Lecture 20 Functional Coverage, Need of Functional Coverage, Functional Coverage Implementation, Functional Coverage Types, Functional Coverage Report Analysis, Code Coverage, Code Coverage Report Generation. 3:52:11
Lecture 21 Code Coverage Analysis, Code Coverage Types, UCDB, Code Coverage Example, Assertions 3:54:57
Lecture 22 Assertion Examples, DPI, Configuration Libraries, packages, Compiler Directives. 3:02:43
Lecture 23 Common array methods, atoi, Callback detailed explanation 2:27:51
Lecture 24 DMA Controller Session1 : DMA Controller specification reading, understanding architecture, design features, registers 03:07:36
Lecture 25 DMA Controller Session2: Feature listing down, test plan creation, testbench architecture, testbench component coding 02:33:41
Lecture 26 DMA Controller Session3: Testbench component coding, testbench integration, register model development 02:53:07
Lecture 27 DMA Controller Session4: Sanity test case bringup, reference model, checker and scoreboard implementation 03:19:14
Lecture 28 DMA Controller Session5: Functional test case coding, debug, update testbench components 02:18:45
Lecture 29 DMA Controller Session6: Functional test case coding 03:02:05
Lecture 30 DMA Controller Session7: Setting up regression, generate regression report, coverage report 03:10:20
Lecture 31 DMA Controller Session8: Analyze coverage report, create new tests, debug newly added tests 01:44:23
Lecture 32 DMA Controller Session9: Coverage analysis, adding new tests for coverage closure 01:44:23
Lecture 33 AXI Protocol overview and features 03:26:12
Lecture 34 AXI channels, signal encoding, timing diagrams 01:49:06
Lecture 35 AXI protocol advanced features 01:42:21
Lecture 36 AXI protocol advanced features 01:05:55
Lecture 37 AXI VIP Development 04:07:08
Lecture 38 AXI VIP Development 04:07:08
Lecture 39 AXI advanced feature checking 00:25:08
Lecture 40 AXI UVC(UVM based) Development 01:08:08
Lecture 41 AXI Interview questions 00:26:08
Lecture 42 AXI interconnect development concepts 00:06:08
Lecture 43 AXI UVC bringup 00:03:12

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