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RISC-V ISA Training

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RISC-V ISA Training

Course Overview

RISC-V is a open ISA based on RISC principles. RISC-V is getting more traction with many companies adopting RISC-V based platforms. RISC-V ISA training focused on all the aspects starting architecture, ISA, instruction summary, memory model, exceptions, privilege model.

Unit Number	Topic	Duration (Mins)
1	Training agenda, processor role in SOC	39
2	Processor architectures, Why RISC-V	21
3	RISCV-ISA	20
4	Load-store-architecture	12
5	Signed-extension	18
6	Program-counter	12
7	procedure	1
8	instruction categories, extensions	32
9	Base instruction format, instruction conversion to hexcode	30
10	Base ISA instructions	67
11	JAL, branch insturctions, control transfer instructions	33
12	Load store instructions	16
13	Understanding immediate value in instructions	19
14	Arithmetic instructions	8
15	Writing assembly instruction coding examples	105
16	Privilege levels	15
17	Control and Status registers	19
18	MMU lecture overview	2
19	MMU page table basics	40
20	mstatus register : Memory Privilege	14
21	MMU address translation	25
22	MMU 2-level page tables	34
23	MMU Page fault	9
24	MMU LPAE	6
25	Exceptions, Traps, Interrupts	13
26	Machine mode introduction, CSRs in machine mode	23
27	mstatus register : interrupt enable bits (MIE, SIE, MPIE, SPIE)	17
28	mstatus register MRET SRET instructions	6
29	mstatus register : Base ISA Control	9
30	mstatus register : Endianness control	7
31	mstatus : Virtualization support	9
32	machine trap vector base address register (mtvec)	9
33	machine trap delegation register	14
34	machine interrupt register	11
35	hardware performance monitors	5
36	Machine counter enable register	6
37	Machine cause register	9
38	Machine level memory mapped registers	3
39	Machine mode privileged instructions	10
40	RISC-V Reset	5
41	Non Maskable Interrupts	5
42	Physical memory attributes	24
43	Memory ordering	11
44	Memory ordering PMAs	9
45	Coherence and Cacheability PMAs	7
46	Physical memory protection	23

Processor significance in SOC
Why RISCV
RISCV ISA
RISCV basics
RISC-V architecture
Sub components
Instruction Fetch unit, Decode unit, execution unit
pipelining stages
Instruction set architecture (ISA)
Instruction summary
- RV32I Base Integer Instruction set
- RV32E Base Integer Instruction Set
- RV64I Base Integer Instruction set
- RV32/64G Instruction set listings
- RISC-V Assembly programming summary
- M Standard Extension for Integer
- Multiplication and Division
- A Standard Extension for Atomic Instructions
- F Standard Extension for Single-Precision Floating-point
- D Standard Extension for Double-Precision Floating-point
Multiple hands on example on RISC-V based code implementation
RV32I base instruction
Exceptions, Traps and Interrupts
Sample examples using RISC-V assembly language
- prime number generation
- Multiple examples on RISC-V assembly instruction coding
RISC-V Privilege levels
Switching between privilege levels
Control and status registers
Machine mode
- Physical memory protection
- Physical memory attributes
Supervisor mode
User mode
MMU
- VA to PA translation
- Page faults
- Translating Virtual Addresses

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Course Instructor

Dedicated Trainer Accessible On Phone / Email / Whatsapp
Trainer Exp: 15 Years

Price - ₹6,000 + GST

₹7,500 (20% Off)

10 hours left to avail at this price

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What Our Students Says About Inskill

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Faculties are well experienced and very helpful.
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10.04.2018

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I joined this institute in summer after I was admissioned into IIT MADRAS, some of my seniors done training in this institute so they suggested me. When I was joining this institute my aim was to learn hardware language so that at the time of placements I should have some extra skills to stand out from the crowd and when the placement came I was so clear about my conceepts and the interviewers got impressed..they provided training live and I was able to clear my doubts and it also helped in courses in IIT which was a hectic thing for others.

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