• SOC design & verification flow overview
• SOC Design concepts
• Processor boot concepts
• SOC Verification: Important aspects
• Testbench
• Setting up SOC TB environment
• SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
• Testplan
• Testcase Flow
• Testcase Coding (C & SV)
• Running testcases & regression
• SOC Test debug
• Typical testcase issues
• Verification closure
• Performance requirements
• Gate level simulations
• Power Aware Simulations
• PAGLS
• EVCD generation
• Vector runs on VT setup
• Generating binaries for running on tester
• ECO
• RMA
• UVC in Testbench setup & sequence usage in SV testcase

SOC FLOW

• SoC Architecture
• Design Integration
• Spyglass
• Functional Verification
• Formal Verification (Connectivity Checks)
• PA RTL simulations
• GLS
• PA GLS simulations (UPF)
• Vector EVCD generation
• VT simulations on testers
• Post silicon validation (VI)

Design

• SoC Architecture
• SoC Interconnects & NOCs
• NoC Overview – Types of NOCs, purpose and diagram
• SoC Digital & Analog Components
• SoC Address Mapping
• SoC Interrupt Mapping
• SoC Frequency Plan
• SoC Performance requirements
• Features
• DPLL
• SoC Memories: Msg ram, Iram, DDR, Flash
• SoC Subsystems
• Low Power Verification
• UPF

Important Aspects

• SoC Architecture, understanding transaction matrix
• Processor boot, SCF file
• Interconnects
• Memory preloading
• DDR initialization
• PLL locking (LMN values)
• TIC interface
• Clock domains
• Different clock modes
• XO mode, at-speed mode
• Interrupt handler
• Processor interfaces (instruction fetch, data code)
• I/Os of SOC: Dedicated IOs, GPIOs
• GPIO purpose: Pad muxing
• CDC
• Cycle slips
• MMU, Physical address, Virtual address
• ARM instruction set basics
• Types of verification and their differences
• Processor architectures: ARM, ARC, DSP
• Cortex A series, M series
• Impact on design architecture
• Basics of ARM processors
• Types of processors – Cortex-M series, A series
• ARM C, ASM compiler, linker
• Caches (L1 and L2)
• Generic Interrupt Controller
• Exceptions, Events – Types and handling
• Debug system – Basics of ARM debug subsystem
• Scatter files
• Setting reset location to start booting
• Loading C code into memories – Front door, back door
• ARM Instruction example

SOC Testbench Setup

• SoC environment structure
• SoC TB Architecture
• Integrating UVC into SoC TB
• SoC Processor-TB interaction

Testplan

• Register wr-rd, reset tests
• Interrupt tests
• Targeting different frequency plans
• Feature (use-case) tests
• Power aware tests
• Fuse tests
• End-to-end data transfer tests
• Booting from different testcases
• Address decoding access tests
• Connectivity tests

Testcase Flow

• TIC mode
• Functional mode
• Device Initialization
• DDR initialization
• Enabling DDR access to different processors
• Processor boot sequence
• Processor boot from different memories
• C test main function
• Power uncollapse
• Functional test

Coding Testcases

• Listing down test requirements, pass criteria
• Power domains to be up
• Clock domains to be up, required frequencies
• Understanding required flow to implement testcase
• Knowing library functions to implement above flow
• Understanding handshake between Native & SV code

Setting up Environment

• Design baseline
• All design sub-component latest baselines
• Verif baseline
• All verif sub-component latest baselines
• Updating environment for custom baseline

Running Testcases & Regression

• Command line
• sim\_gui mode
• Command line options
• Using force files, timing corners, frequency plans

Debugging Tests

• Tarmac log
• List file
• MPF file
• Log
• Wave dump debug
• Message-based debug
• Warnings, errors

Typical Testcase Issues

• Processor not booting
• Register looping
• Not working at current frequency plan
• PLL not locked
• Memory not preloaded
• Clocks not running
• Access not enabled to register or memory space
• Simulation not proceeding in time
• Simulation proceeding but not completing (looping)
• Interrupt not serviced
• Interrupt not generated
• Signal not sampled
• Sub-module functional issues
• Denali errors
• Memory loading ‘x’ debug
• Tied signals, unconnected ports

Understanding Chip Stages

• RTL code freeze
• Base tapeout
• Metal tapeout
• ECO update
• CS (customer shipment)
• RMA

Verification Closure

• Regression 100% pass
• 100% toggle coverage
• High level & low-level reviews
• Performance requirements
• Power requirements met

Gate Level Simulations

• Significance
• Choosing tests for GLS

EVCD Generation

• Format
• Purpose
• Choosing tests for GLS

Vector Runs on VT Setup

• Production vectors
• Characterization vectors

Generating Binaries for Running on Tester

• Vector debug

ECO

• When ECO is issued

RMA

• Significance

Misc – SoC Architecture Topics

• SoC Interconnects
• SoC Digital & Analog Components
• SoC Address Mapping
• SoC Interrupt Mapping
• SoC Frequency Plan
• SoC Performance requirements
• Features
• PLL
• SoC Memories: Msg ram, Iram, DDR, Flash
• Processor booting from different memories
• UVC in Testbench setup & sequence usage in SV testcase