Custom layout training is 4.5 months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a layout design engineer in various aspects of layout including analog layout, memory layout, standard cell layout and io layout. Custom layout design course ensures that a fresher/experienced engineer is prepared on all the essential aspects of Custom layout including ASIC flow, VLSI Design flow, Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO's and detailed analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Majority of graduates lack good foundation in digital and analog design concepts, make them under prepared for industry requirements. Custom layout training will enable the candidate for job opportunities within 3 months from the start of course. Complete 4.5 months training ensures that the candidate is an expert in the domain.
Course includes 20+ detailed labs & assignments covering all aspects of custom layout with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchoff law's, Diode-operation, MOSFET's, MOSEFT operations, second order effects, FinFET's, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures. Followed by various analog layout techniques with detailed discussion on Mismatches & Matching, Noises & Coupling, various failure mechanisms which includes Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD.
Analog layout techniques will involve multiple hands on projects covering various concepts such as common centroid, inter digitation, resistor matching, capacitor matching and opamp circuits, current mirrors, PLL's, ADC's, DAC's, Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines, Large drivers, LNA & Mixers, and Sense amplifier & Bit cell development.
Uniy Number | Topic | Duration (Mins) |
1 | Network theory, KVL, KCL Voltage division rule, current division rule | 75 |
2 | Continuation and classification of materials. | 80 |
3 | MOSFET, Cross sectional view of NMOS, Boolean expression schematic, XOR schematic, cross sectional view of CMOS | 80 |
4 | Tool access and schematic of Inverter, PMOS layout. | 88 |
5 | CMOS fabrication process | 44 |
6 | Level shifter schematic, multiplexer using transmission gate | 67 |
7 | Schmitt trigger using CMOS theory | 51 |
8 | PMOS layout and bind keys | 92 |
9 | Inverter schematic and layout | 84 |
10 | Continuation of Inverter layout and NAND, NOR, ExOR schematic | 77 |
11 | Inverter layout doubt clarification session | 81 |
12 | Level shifter schematic, stick diagram and Layout | 69 |
13 | Level shifter schematic, stick diagram and Layout | 90 |
14 | NAND and NOR Layout practice | 83 |
15 | MUX (2x1) using CMOS, Schematic and XOR schematic, Stick diagram, Current mirror | 87 |
16 | LAYOUT SES16 | 80 |
17 | LAYOUT SES17 | 73 |
18 | LAYOUT SES18 | 97 |
19 | LAYOUT SES19 | 82 |
20 | LAYOUT SES20 | 87 |
21 | LAYOUT SES21 | 84 |
22 | LAYOUT SES22 | 100 |
23 | LAYOUT SES23 | 94 |
24 | LAYOUT SES24 | 85 |
25 | LAYOUT SES25 | 77 |
26 | LAYOUT SES26 | 86 |
27 | LAYOUT SES27 | 81 |
28 | LAYOUT SES28 | 83 |
29 | LAYOUT SES29 | 53 |
30 | LAYOUT SES30 | 75 |
31 | LAYOUT SES31 | 65 |
32 | LAYOUT SES32 | 71 |
33 | LAYOUT SES33 | 39 |
34 | LAYOUT SES34 | 40 |
Specification |
RTL coding, lint checks |
RTL integration |
Connectivity checks |
Functional Verification |
Synthesis & STA |
Gate level simulations |
Power aware simulations |
Placement and Routing |
DFT |
Custom layout |
Post silicon validation |
Digital Design basics |
combinational logic |
sequential logic, FF, latch, counters |
Memories |
Refer to Advanced digital design training page for detailed course contents |
www.vlsiguru.com/digital-design-complete |
Linux/UNIX OS, Shell |
Working with files, directories |
Commonly used commands |
Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor |
Basic Passive and Active devices |
Ohms law, Kirchoff laws |
Basic of circuit understanding |
MOSFET Basics, Operations, few simple circuits & second order effects. |
MOSFET Detailed fabrication process. |
FinFET working, Fabrication, advantages & disadvantages. |
Layout Editor Tool |
Understanding the schematic symbols and parameters |
Creating and managing libraries and cell |
Commands for Layout editing. |
Commands for schematic editing. |
Verification : DRC and LVS |
Antenna effect, latchup, Electromigration, IR Drop |
Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC |
Resistor, Capacitor layout techniques |
CMOS and BiCMOS layout techniques |
Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop |
Mismatches & Matching. |
Failure Mechanism : Electro migration, IR drop, LOD & Stress effects, WPE, Antenna Effects, Latch up, ESD (with High voltage rules, EOS effects). |
Noises & Coupling. |
Different Types of process - Advantages & Disadvantages - Planar CMOS, FD-SOI, SOI, Bi-CMOS, Gallium Arsenide, Silicon-Germanium, Finfet. |
Full Chip Construction, Scribe Seal, Pad Frame, Integration and guidelines. |
Packaging |
Std Cell & Memories. |
IO Layout Guidelines : High speed IOs and High Speed Interfaces. |
Sense amplifier & Bit cell development |
Why memory layout different than analog layout |
Memory layout flow |
Types of memory layout (SRAM/DRAM/ROM) |
Introduction to SRAM memory layout |
Fixing few manually created leaf-cell errors which impact |
Abutment issues |
SRAM memory design architecture |
Words line and address line |
SRAM rows and column design |
Building blocks of SRAM |
Memory Bit cell |
Row decoder |
Word line driver |
Sense amplifier |
Control block |
Misc digital logic. |
Pitch Calculation for blocks. |
Power Planning |
High speed Analog Layout |
RF Layout guidelines with Transmission lines and inductor concepts |
Handling clocks |
Analog Circuits & Layout guidelines |
Single & Multi stage differential opamp layout |
current mirror layout |
PLL, DLL and Oscillators |
LDO and other regulators |
ADCs & DACs |
Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines |
Large drivers. |
LNA & Mixers. |
input pair, differential routing, Power routing, offset minimizing |
Power/Signal IR Drop |
cross-talk and coupling |
Electrostatic Discharge |
Deep Submicron Layout Issues |
Shallow Trench Isolation (LOD) |
Well Proximity Effect. |
Design Rule Checks |
Layout Versus Schematic (LVS) |
Electrical Rule Checks (ERC) |
Antenna Checks |
Latch-up |
Reliability checks like EM and IR analysis |
Design for manufacturability (DFM)checks |
Electrostatic discharge (ESD) path checks |
Assignments and multiple hands on projects |
Best Practices & Interview Questions. |
TESTIMONIALS
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.
I have taken training at VLSIGURU for Design and Verification course through online.
They have very experienced faculty with industrial knowledge.
The trainers explained every concept from the very basic to core concepts with good explanation.
Every doubt has been clarified with patience and in detail.
Every session os recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provided online access as well.
VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts.
Interview preparation sessions has also been conducted along with mock interviews and training sessions.
It is the best institute to gain knowledge in core domain with affordable prices.
I Thank VLSIGURU for helping me to gain knowledge in the core domain.
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