TCL for VLSI flow automation training
Application Oriented TCL for Synopsys ToolsTCL training is for VLSI professionals and students who work on Synopsys tools like ICC/ICC2 Compiler, DFT Compiler, Design Compiler , Primetime.
- 53 HoursCourse Duration
- 51 SessionsRecorded & Live
- 4.6/5Learner Rating
- 650+Enrolled Learners
Course Overview
About Course
Application Oriented TCL for Synopsys Tools
TCL training is for VLSI professionals and students who work on Synopsys tools like ICC/ICC2 Compiler, DFT Compiler, Design Compiler , Primetime. Training will enhance your scripting skills which increase your productivity while using Synopsys tools. Real time Projects/Assignments will be given to audience as well as driven by audience requirements.Explanation and Execution of all concepts, commands and scripts will done in ICC shell to connect to audience requirements. VPN will be given to audience for practice and execution of projects/assignments. Tools Used for TCL Scripting : ICC2, Primetime, Design Compiler
All the EDA tool flows from Synopsys, Cadence and Mentor Graphics use Tcl as the primary scripting interface for their flows. TCL as a single command language in all EDA tool flows ensures that a designer only needs to learn Tcl in order to work with all the flows.
TCL scripting is much sought after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.
Detailed Syllabus
4 modules- Overview
- Env Setup
- Special Variables
- Data Types
- Variables
- Operators
- Decisions
- Loops
- Arrays, Strings, Lists, Dictionary
- History and Redoing of commands
- String Pattern Matching commands
- Unit 1: File Operations
- Lab 1: Scripts on file operations.
- Unit 2 : Usage of redirect command
- Lab 2 : Execution of redirect commands
- Unit 3 : Control Flow, Math Functions
- Lab 3 : Execution of Control Flow, Maths Functions.
- Unit 4: Procedures
- Lab 4 : Writing own Procedural commands.
- Unit 5: Procedures with positional arguments
- Lab 5: Writing own Procedures with positional arguments
- Unit 6 : Procedures with non positional arguments (switch based procedures)
- Lab 6 : Writing own Procedures with non positional arguments.
- Unit 7: Object Classes and Design Objects
- Lab 7 : Commands to handles design objects
- Unit 8 : Collections
- Lab 8 : Commands to handle Collections
- Unit 9 : Design objects Collection and its attributes
- Lab 9 : Scripts on collections and its attributes
- Unit 10 : Linking design objects with another design objects.
- Lab 10: Scripts on linking design objects with another design objects.
- Unit 11 : Filtering applications on design objects.
- Lab 11 : Scripts on filtering applications
- Lab 12: Script to get gate count of full chip.
- Lab 13: Script for macro placement.
- Lab 14: Script for finding high fan out nets
- Lab 15: Script on ECO fixing like inserting buffers on high fan out nets
- Lab 16: Script on inserting antenna diodes to fix antenna violations.
- Script to write customize pin placement.
- Script to write TCL file to execute some set of command from the collection (it can be a file or variable).
- Script to find shorted (nets having shorts) nets.
- Script to improve the routing of bad nets.
- Script to insert buffer to all endpoints having hold violations.
- Script to resolve overlapping even after legalize placement.
- Script for handling logs from different Synopsys tools.
- Script to report endpoints and start points slack of top 1000 failing paths
- Script to get a list of the register sinks for a clock
- Script to return all the instance pins that are in timing path.
- Script to report slack and difference between clock arrival time at launch and capture clocks.
- Script to report logics between reg to reg path. This script can be modified for different path groups.
- Script to find the number of logic levels(combinational) in a timing path or group of timing paths.
- Script to report worst slack for all clock group.
- Dedicated projects based on audience requirements
- Assignments based on TCL flow automation for various aspects of VLSI backend flow.
Session-wise Content
51 sessions · 51h 55m- 1TCL Cygwin usage basics20m
- 2TCL TRAINING OVERVIEW, AGENDA20m
- 3Introduction to TCL40m
- 4How to run the TCL program58m
- 5Formal syntax of the TCL50m
- 6set, puts and gets commands36m
- 7Escape characters56m
- 8TCL Operators1h 27m
- 9TCL Control statements58m
- 10TCL Control statements (if and for statements)1h 3m
- 11TCL Control statements (while statements)31m
- 12TCL Control statements (switch and foreach statements)30m
- 13TCL strings and its operators24m
- 14Strings operators Conti...1h 8m
- 15Examples of Strings operators Conti...1h 4m
- 16Programs on TCL Strings operators55m
- 17TCL Lists26m
- 18Programs on TCL Lists55m
- 19TCL special variables1h
- 20Programs on TCL special variables30m
- 21Programs on TCL special variables Conti...35m
- 22TCL File handling operations54m
- 23Programs on TCL File handling operations59m
- 24Programs on TCL File handling operations Conti...56m
- 25TCL Procedures and Programs on TCL Procedures1h 22m
- 26TCL Procedures and Programs on TCL Procedures Conti...50m
- 27TCL Procedures and its parameters52m
- 28Ses 11 P 2 TCL Arrays32m
- 29TCL Associative Arrays47m
- 30Programs on TCL Arrays33m
- 31TCL Dictionary1h 5m
- 32TCL Regular expression48m
- 33Programs on TCL Regular expression48m
- 34Programs on TCL Regular expression Conti...46m
- 35Programs on TCL Regular expression Conti...46m
- 36TCL ADVANCED SES1 Tool Installation and Design Access1h 17m
- 37TCL ADVANCED SES2 ICC2 Commands Understanding Objects , class , attributes2h 14m
- 38TCL ADVANCED SES3 TCL program to find core area for any utilization1h 47m
- 39TCL ADVANCED SES4 TCL program to place ports at particular locations2h 23m
- 40TCL ADVANCED SES5 Multi votage design and TCL program to create voltage area2h 16m
- 41TCL ADVANCED SES 8 Automated TCL code to fix max_cap and max_trans1h 25m
- 42TCL ADVANCED SES 9 Report timing and TCL script on timing reports2h 53m
- 43TCL ADVANCED SES 6 TCL Prgram for padding to spread cells.mp458m
- 44TCL ADVANCED SES 7 TCL Prgram for Upsizing driver and inserting buffer to driver pin of violated net to fix DR2h
- 45TCL ADVANCED SES 10 TCL scripts for implementing Usefull skew method53m
- 46TCL ADVANCED SES 11 TCL script for getting shorted nets and fixing it1h 10m
- 47TCL ADVANCED SES 12 TCL code to get open clock pins after CTS44m
- 48TCL ADVANCED SES 13 Whether all clock pin has clock gating cells or not50m
- 49TCL ADVANCED SES 14 Applying keepout margin around the cells to fix keepout margin29m
- 50TCL ADVANCED SES 15 To get Bottle neck cells1h 48m
- 51TCL ADVANCED SES 16 Get slack values of neighbouring cells . This is helpful in IR drop fixing44m
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What Our Students Say
Frequently Asked Questions
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts