UVM Functional Verification Training & Online Courses

Unit Number	Topic	Duration (Mins)
1	UVM TB Simulation on EDA PLAYGROUND	19
2	Agenda, course schedule	11
3	What is UVM	17
4	Need for methodology	43
5	UVM overview, OOP basics	27
6	UVM TB architecture	14
7	Factory basics	12
8	UVM TB example	49
9	Memory TB development	115
10	Memory TB development : Coverage, Monitor	87
11	Memory TB development : Testcase coding	137
12	UVM Questions	60
13	Doubts, Sequence layering	70
14	UVM Root	31
15	objection basics	20
16	revision, UVM base classes	30
17	Command line processor	21
18	Student Doubt Clarification	3
19	UVM TB example contd, Objections	149
20	revision, Question-answers	55
21	reporting classes	58
22	UVM phases	30
23	UVM command phases - Question & answers	16
24	Factory:	19
25	Factory (uvm_factory)	19
26	Revision	62
27	UVM scheduled phases - run sub phases	3
28	Factory, TB Development	88
29	UVM config DB	80
30	question - answers and revision	16
31	configuration database (config_db)	50
32	resource db	109
33	TLM Basics, TLM Push model	48
34	revision, questions, config_db	24
35	TLM TB connection types	23
36	TLM Connection assignment solution	61
37	TLM - Pull, FIFO and Broadcast model	82
38	TLM TB connection types	22
39	TLM Connection assignment solution	61
40	Driver - Sqr communication	17
41	Test library, Sequnece library, Sequence-Sequencer relation	84
42	default_sequence in UVM sequencer	22
43	sequence, virtual sequencer	32
44	Virtual sequencer and virtual sequences	111
45	UVM doubt clarification	47
46	Asynchronous FIFO UVM TB Development	107
47	Asynchronous FIFO TB : Scoreboard development, virtual sequencer	80
48	APB	39
49	APB UVC and TB template development	44
50	APB UVC sequence and test case coding and debug	66
51	AHB protocol introduction	6
52	AHB protocol basics	19
53	AHB Basics, AHB system architecture	15
54	AHB transfer phases	16
55	Handshaking	7
56	Arbitration phase	14
57	AHB transfer timing diagrams	31
58	Signal decoding	26
59	AHB transaction example	10
60	AHB Burst transfers	16
61	AHB features, aligned transfers, wrap transfers	58
62	Questions, revision	32
63	Features: Address decoding	15
64	AHB master signals	20
65	AHB features: Early burst termination	8
66	Two cycle response	8
67	AHB arbitration, Split, retry	28
68	Exclusive transfers	17
69	AHB UVC: Type of UVC, TB Development using UVC	18
70	AHB UVC template development	15
71	AHB UVC functional development	13
72	revision, questions, AHB transaction coding advanced aspects	50
73	AHB Driver coding	69
74	AHB Responder coding	32
75	AHB monitor coding:	36
76	AHB interface coding	44
77	revision, AHB responder update, AHB UVC issue summary	33
78	question, answers	8
79	AHB UVC issue debugging	112
80	AHB UVC scoreboard coding	33
81	Assertion coding for AHB protocol	16
82	AHB UVC - Implementing functional testcases	30
83	Developing more functional testcases	60
84	AHB interview questions	15
85	Revision, AHB interconnect SOC and IP level verification overview	6
86	AHB Sequence library	50
87	AHB LITE UVC Development	26
88	AHB interconnect verification	212
89	Revision, AHB I/C feature listing down	20
90	AHB scoreboard	110
91	UVM advanced topics, revision	16
92	Different types of sequences	88
93	Different styles of sequence coding	55
94	Virtual sequencer and virtual sequences	111
95	Sequence execution: UVM scheduled phases	30
96	UVM doubt clarification	47
97	interview questions	15
98	TLM2.0	120
99	Synchronization classes	77
100	UVM callbacks	45
101	UVM heartbeat	52
102	UVM report catcher	23
103	revision, phase jumping	55
104	policy classes	78
105	UVM RAL - Register model	168
106	Register Model usage	111
107	USB Register model coding	62

UVM Advanced training with 2 hands on projects

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UVM Advanced training with 2 hands on Projects

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Curriculum

1 : Verification Methodologies: UVM & OVM

2 : AHB UVC Development

3 : AHB Interconnect Functional Verification

4 : USB2.0 Register Layer

5 : Course Assignments

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