advanced physical design training
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Advanced physical design training
- Course Duration: 120 Hours
- 4.6 Star (Rating)
- 3000 (Student Enrolled till Now)
Advanced Physical Design Training – Course Overview
About the Course
Advanced Physical Design Training is a comprehensive e-learning program designed for working professionals to gain in-depth knowledge of the complete VLSI physical design flow from netlist to GDSII at advanced technology nodes such as 14nm and 28nm. The course assumes that learners are familiar with fundamental concepts of CMOS, digital design, and semiconductor fabrication.
This program provides detailed exposure to all stages of the backend VLSI flow, including floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff. Learners gain practical experience through multiple hands-on projects using industry-standard Synopsys tools such as Design Compiler (DC), IC Compiler II (ICC II), StarRC, PrimeTime (PT), and IC Validator (ICV). The Synopsys physical design flow is widely adopted in the semiconductor industry and forms the basis of this training.
The course emphasizes real-world challenges faced in industry-level physical design projects and focuses on effective strategies to resolve timing, congestion, and power integrity issues. In addition to physical implementation, the training also covers important backend concepts such as synthesis, IR drop analysis, and physical verification. This program equips participants with end-to-end expertise in the VLSI backend flow, enabling them to meet diverse job role requirements in physical design and backend implementation teams.
Course Objectives
The primary objectives of this course are to:
• Build strong understanding of complete physical design flow from netlist to GDSII
• Gain expertise in floorplanning, placement, CTS, routing, and timing closure
• Learn to use industry-standard Synopsys tools for backend implementation
• Understand parasitic extraction and timing signoff methodologies
• Analyze and resolve congestion, timing, and power integrity issues
• Learn IR drop analysis and physical verification concepts
• Develop hands-on experience through real-world backend design projects
• Prepare learners for physical design and backend VLSI job roles
| Session Number | Topic | Duration (Mins) |
| 1 | ASIC Design flow | 149 |
| 2 | Factors affecting delay and Power in CMOS | 126 |
| 3 | Input file - .lib file | 106 |
| 4 | Input file - .lef file | 72 |
| 5 | Input file - .tf and tlu+ file | 75 |
| 6 | Netlist and Hireachial design | 90 |
| 7 | Creating Core area and Die Area | 92 |
| 8 | Port Placement | 43 |
| 9 | TCL Program for Port Placement using Different Commands | 97 |
| 10 | Macros and Type of Macros | 121 |
| 11 | Macro Placement Guide lines | 46 |
| 12 | Blockages and Keepout Margin | 30 |
| 13 | Power Reduction Techniques - Multi Voltage design | 37 |
| 14 | Power Reduction Techniques - Multi Vt Cells | 10 |
| 15 | Power Reduction Techniques - Clock gating Design | 13 |
| 16 | UPF For Multivoltage design | 87 |
| 17 | Power Reduction Techniques - Power gating design | 71 |
| 18 | End cap cells | 35 |
| 19 | TAP cells , TIE Cells DCAP and Spare cells | 85 |
| 20 | Power Planning | 92 |
| 21 | Sanity Checks at each stage and basics of timing | 184 |
| 22 | Setup and Hold Analysis | 56 |
| 23 | In to reg and reg to out path discussion | 141 |
| 24 | PBA and GBA paths | 115 |
| 25 | Timing Exceptions | 67 |
| 26 | Uncertainity , Skew , transition and Driving cell | 81 |
| 27 | Placement goals and checks before placement stage | 92 |
| 28 | Inputs to placement and Placement steps | 120 |
| 29 | Placement Optimization Techniques | 189 |
| 30 | CTS and Clock gating cells | 123 |
| 31 | CTS spec and Clock tree exceptions | 98 |
| 32 | CTS steps and CRPR | 141 |
| 33 | Multisource and Checks after CTS | 75 |
| 34 | Routing | 130 |
| 35 | Signoff checks | 101 |
| 36 | Revision & Interview preparation | 121 |
| 37 | Revision & Interview preparation | 144 |
| 38 | Revision & Interview preparation | 46 |
| 39 | Revision & Interview preparation | 128 |
Curriculum
| Specification |
| RTL coding, lint checks |
| RTL integration |
| Connectivity checks |
| Functional Verification |
| Synthesis & STA |
| Gate level simulations |
| Power aware simulations |
| Placement and Routing |
| DFT |
| Custom layout |
| Post silicon validation |
| Conductors, Semiconductors, Insulators |
| Intrinsic and Extrinsic Semiconductors |
| Diode |
| BJT |
| MOSFET (NMOS, PMOS, CMOS) |
| FinFET |
| Device Fabrication |
| Significance of above aspects with Physical Design flow |
| Shells |
| File and directory management |
| User administration |
| Environment variables |
| Commonly used commands |
| Shell scripting basics |
| SEd and AWK |
| Revision management |
| Makefiles |
| Digital Design basics |
| combinational logic |
| sequential logic, FF, latch, counters |
| Memories |
| Setup time, Hold time, timing closure, fixing setup time and hold time violations |
| STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations |
| www.vlsiguru.com/digital-design-complete |
| Introduction to all the majorly used keywords on PD flow |
| VLSI Technology concepts |
| Resistance, Capacitance, Inductance |
| Parasitic capacitance |
| L-C-R circuit analysis |
| RC circuit significance with circuit delay |
| Clock distribution concepts, skew |
| Introduce TCL |
| Why TCL? |
| TCL Script Processing |
| Understand TCL uses and strengths |
| Writing simple TCL scripts |
| TCL for VLSI scripting |
| TCL : Main Features |
| TCL in EDA |
| TCL shell (tclsh) |
| Working with TCL scripts (UNIX) |
| TCL Interpreter in SoC Design Tools |
| TCL Scripting for SoC Design |
| TCL Commands |
| Variables |
| Substitution and Command Evaluation |
| Operators |
| Mathematical Functions |
| Procedures |
| Control flow : if, if-else, switch, for, foreach, while, break and continue |
| string, string operations |
| List, List manipulation |
| Arrays, array methods |
| Working with files |
| Command line arguments |
| Regular expressions |
| Complete TCL Scripts |
| TCL Packages |
| Basics of Synthesis |
| High Level Synthesis Flow |
| Reading of Verilog RTL File |
| Target and Link Libraries |
| Resolving References with Link Libraries |
| Reading hierarchical Designs |
| Reading ddc design |
| Analyse & Elaborate Commands |
| Constraining and Compiling RTL |
| Post Synthesis Output Data |
| Constraining Register to Register Paths |
| Constraining Inputs Paths |
| Constraining Outputs Paths |
| Virtual Clock |
| Load Budgeting |
| Default Path Groups |
| Creating User-defined Path Groups |
| Prioritizing Path Groups |
| Timing Reports |
| Analyzing Timing Reports |
| Defining a Clock with additional options |
| Input Delay with additional options |
| Output Delay with additional options |
| Pre-CTS versus Post CTS Clock Latencies |
| Independent IO Latencies |
| Output Delay with Network Latency |
| Output Delay with Source Latency |
| Different IO versus Internal Latencies |
| IO Clock Latencies |
| Handling Different IO Vs Internal Latencies |
| Virtual External Clock Latencies |
| Included External Clock Latencies |
| Multiple Synchronous Clocks |
| Multiple Clocks Input Delay |
| Maximum Internal Input Delay |
| Multiple Clock Output Delay |
| Maximum Internal Output Delay |
| Inter Clock Uncertainty |
| Generated Clocks |
| Mutual Exclusive Synchronous Clocks |
| Logically Exclusive Clocks |
| Multiple Clocks per Register |
| Cross Talk Analysis |
| Asynchronous Clocks |
| Multi Cycle Paths and Constraints |
| High Level Multi-Voltage Design Concepts |
| Supplies and Power Domains |
| Power Ports and Nets |
| Level Shifters |
| Power States and PS Table |
| IC Compiler II Library Manager |
| ICC Compiler II NDM Cell Library |
| Cell Library Characteristics |
| Library Manager Flow |
| Tech Only NDM Library |
| Technology-Only Library Flow |
| Technology File |
| Read TLU+ Files |
| Tech Library Preparation |
| Top Level, Sub-System Level and Block Level Design Setup |
| Set up initial Design Implementation |
| Loading Netlist from Synthesis |
| Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files |
| Flow Setup and Design Setup |
| Loop-back to Synthesis for Correlation issues correction |
| Top Level, Sub-System Level and Block Level Design Setup |
| Set up initial Design Implementation |
| Loading Netlist from Synthesis |
| Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files |
| Flow Setup and Design Setup |
| Loop-back to Synthesis for Correlation issues correction |
| Initial Floorplanning settings |
| Define Pad Instances (Physical Cells) |
| Pad Instance co-ordinates |
| Start Floorplaning |
| Core Die Size setting |
| Floorplanning of Pad Instances |
| Pad Filler Insertion |
| Define Pad Ring Power Grid |
| Macro Instance constraints |
| Macro Instance Array creation |
| Macro Instance Orientation |
| Anchor based and Relative Placement of Macro Instances |
| Macro Instance-Channel settings |
| Macro Instance placement - Manual |
| Congestion probability around Macro Instances |
| Defining Placement Blockages |
| Running placement |
| Defining placement strategies |
| In Place Optimization |
| Hierarchical Placement |
| Relative Placement |
| Congestion analysis and reduction |
| Macro placement changes to reduce congestion |
| Standard Cell Placement Constraints |
| Halo creation for instances |
| Congestion Analysis with Standard Cell placement |
| Local Congestion Reduction |
| Density Screen and Placement Blockage for Standard Cells |
| Congestion Aware Placement |
| Re-Check Macro Placement for better Congestion relief |
| Create Balanced Buffer Trees for High Fanout Net |
| Defining Power Structure |
| Logical Power/Ground Connections |
| Setting Power Network Constraints |
| Create and Analyze Power Structure |
| Change Power Constraints and Re-Createto meet IR requirements |
| Power Ground Pin connection and create Power Rails |
| Power Network Checks for IR and Resistance |
| Placement Blockage for Power Network |
| Incremental Placement |
| Re-Order Scan connectivity within Chain |
| Re-Partition Scan connectivity across Chains |
| SCANDEF file based Scan Chain Re-Ordering |
| Congestion checks for Overflow again |
| RC extraction for Net Parasitics |
| Check Timing for Max Analysis |
| Run Timing/Congestion aware Placement |
| Logic Re-Structuring for Placement and Timing |
| Check Pre-CTS timing based on Global Routing and Detailed Placement |
| Setting Clock Constraints such as Target Skew Target Insertion Delay |
| Clock Root Attributes as Stop, Float and Exclude Pins |
| Building for Generated and Gated Clocks |
| Don't Touch attribute on existing Clock Tree structure |
| Defining Clock Buffers and Inverters. |
| Set Clock Tree Timing DRCs. |
| Non-Default Clock Routing rules setting |
| Perform Clock Tree Synthesis and Clock Tree Optimization |
| Reduce Hold Violations in Data paths and Scan Paths |
| Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners |
| Synchronous Clock Balancing |
| Cross-Clock Delay Balancing |
| Logical Hierarchy aware CTS |
| Max and Min Analysis and subsequent Optimization |
| Fixing Violations |
| CTS Optimization across other modes and PVT corners (MMMC) |
| Skew and Insertion Delay checks |
| Checking Crosstalk on Clock Network |
| Pre-Route check points |
| Routing fundamentals |
| Global Route |
| Detail Routing |
| Track Assignment and Route |
| Refining Detailed Route |
| Over the Macro routing |
| Non-Preferred Routing direction |
| Clock Net Routing |
| Initial Data path routing |
| Redundant VIA insertion setting |
| Post Detailed Route Optimization |
| Fixing DRC Violations |
| Post Detailed Route Delay Calculation Algorithms |
| Crosstalk Delay and Noise Analysis and Fix |
| Check Leakage Power Dissipation |
| VT Cell swap for power and timing trade-off |
| Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD |
| Reduce Dynamic power |
| Meet Total Power target |
| Functional ECO |
| Timing ECO |
| Metal Only ECO using Spare Cells for base frozen designs |
| 2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification |
| Projects based on multi voltage domain |
| Student will be working on 3rd project independently with trainer/mentor support. |
| Antenna Rules and Fixes |
| Critical Area Analysis |
| Wire Spreading and widening |
| Setting minimum metal jog length |
| Filler Cell Insertion |
| Metal Fill |
| Timing Checks after Metal Fill |
| Parasitic Extraction for SignOff timing analysis |
| Export Netlist |
| Export GDSII |
| Facing interviews effectively |
| Industry work culture |
| Group discussions |
Benefits of eLearning?
- Access to the Instructor - Ask questions to the Instructor who taught the course
- Available 24/7 - VLSIGuru eLearning courses are available when and where you need them
- Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
- Sreenivas Reddy — Founder, VLSIGuru
Course Highlights
- 1-1 mentor support
- Mentor guidance support for assignments
- Multiple mock interviews
- Dedicated live support sessions over weekends
TESTIMONIALS
What Our Students Says About Inskill
I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast
VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others
I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.
I have taken training at VLSIGURU for Design and Verification course through online.
They have very experienced faculty with industrial knowledge.
The trainers explained every concept from the very basic to core concepts with good explanation.
Every doubt has been clarified with patience and in detail.
Every session os recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provided online access as well.
VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts.
Interview preparation sessions has also been conducted along with mock interviews and training sessions.
It is the best institute to gain knowledge in core domain with affordable prices.
I Thank VLSIGURU for helping me to gain knowledge in the core domain.
FAQ
Digital and anlog design concepts
- Session notes
- Lab documents with
- detailed steps
- User guides