advanced physical design training

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Advanced physical design training

  • Course Duration: 80 Hours
  • 4.6 Star (Rating)
  • 3000 (Student Enrolled till Now)
Advanced Physical Design Training – Course Overview

 

About the Course

Advanced Physical Design Training is a comprehensive e-learning program designed for working professionals to gain in-depth knowledge of the complete VLSI physical design flow from netlist to GDSII at advanced technology nodes such as 14nm and 28nm. The course assumes that learners are familiar with fundamental concepts of CMOS, digital design, and semiconductor fabrication.

This program provides detailed exposure to all stages of the backend VLSI flow, including floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff. Learners gain practical experience through multiple hands-on projects using industry-standard Synopsys tools such as Design Compiler (DC), IC Compiler II (ICC II), StarRC, PrimeTime (PT), and IC Validator (ICV). The Synopsys physical design flow is widely adopted in the semiconductor industry and forms the basis of this training.

The course emphasizes real-world challenges faced in industry-level physical design projects and focuses on effective strategies to resolve timing, congestion, and power integrity issues. In addition to physical implementation, the training also covers important backend concepts such as synthesis, IR drop analysis, and physical verification. This program equips participants with end-to-end expertise in the VLSI backend flow, enabling them to meet diverse job role requirements in physical design and backend implementation teams.

Course Objectives

The primary objectives of this course are to:

• Build strong understanding of complete physical design flow from netlist to GDSII
• Gain expertise in floorplanning, placement, CTS, routing, and timing closure
• Learn to use industry-standard Synopsys tools for backend implementation
• Understand parasitic extraction and timing signoff methodologies
• Analyze and resolve congestion, timing, and power integrity issues
• Learn IR drop analysis and physical verification concepts
• Develop hands-on experience through real-world backend design projects
• Prepare learners for physical design and backend VLSI job roles

 

 
Unit Number Topic Duration (Mins)
1 Introduction to digital system 25
2 Number system introduction and Radix conversion 61
3 Compliments of the number systems and 1 s and 2 s Compliments 93
4 9 s and 10 s Compliments, 7 s and 8 s Compliments and 15 s and 16 s Compliments 65
5 Gates and its truth table and Why NAND is preferred over NOR gate 72
6 NAND and NOR Realization 67
7 SOP and POS form, minterm, Maxterm canonical SOP and POS form 56
8 Boolean equations Switching equations 26
9 Boolean minimization techniques and K -map(2-variables,3-variables,4-variables) and Logisim tool introduction 100
10 Implicants, PI, EPT, NEPT and RPI 55
11 K -map(5-variables,6-variables) 26
12 K -map with don t care functions 27
13 Building of combinational logic circuits (code converters) 50
14 Code converters continues 43
15 Arithmetic circuits (HA, FA and Parallel Adder) 64
16 Subtractors using compliments (HS, FS) 62
17 MSI circuits (Multiplexers) and Gates using Muxs 67
18 Boolean function Implementation using Mux 53
19 FA using Mux and Mux tree 62
20 Demultiplexers 42
21 Decoders 41
22 Decoders configurations and priority encoders 62
23 Comparators 57
24 Introduction to sequential logic ckts, Basic storage element (NOR latch) 69
25 NAND latch 45
26 Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems 84
27 Master-Slave combination and Edge triggering Flip flops 73
28 Revision of latch, Clocked SR latch, Clocked D latch, Clocked JK latch, Clocked T latch, Racing problems 59
29 Master-Slave combination and its limitations 7
30 Edge triggering and its advantages 51
31 Asynchronous inputsOverriding inputs of Flip flops, Characteristic equations and Excitation table of Flip flops 65
32 Flip flop conversions 18
33 Applications of the Flip flops (Counters - Asynchronous up and down counters) 68
34 Asynchronous Mod-N counters 60
35 Asynchronous updown counters, Timing considerations of the flip flops and limitations of the Asynchronous counter 51
36 Design of synchronous counters 87
37 Registers, shift registers and its configurations, universal shift registers 62
38 Counters based on shift registers (Ring and Johnson counters) 51
39 Frequency divider circuits 101
40 Frequency multiplier and Edge detector circuits 36
41 Introduction to FSM, Implicit and Explicit FSM 63
42 FSM sequence detector of melay and moore model 102
43 Problems on FSM 82
44 Assignment discussion 34
45 Synchronizers to change the pipelining. 25
46 Synchronizers to change the pipelining. 102
47 FSM-Mealy and moore problems,doubt discussion 26
48 D Flip flop using transmission gate 165
49 ASIC FLOW SES1 171
50 ASIC FLOW SES2 148
51 ASIC FLOW SES3 170
52 ASIC FLOW SES4 105
53 UNIX SES1 125
54 UNIX SES2 140
55 UNIX SES3 127
56 UNIX SES4 50
57 UNIX SES5 172
58 UNIX SES6 168
59 UNIX SES7 156
60 UNIX SES8 116
61 UNIX LAB SES 87
62 UNIX LAB SES 129
63 LINUX GVIM SES 32
64 Need for Transistor? 25
65 How MOSFET function? 36
66 Classification of solids. What makes semiconductor special? 26
67 Intrinsic and Extrinsic semiconductors 33
68 PN Junction diode 20
69 Applications of Diode 52
70 BJT 62
71 FET basics 54
72 MOSFET: PMOS, NMOS, CMOS 60
73 CMOS fabrication 102
74 CMOS short channel effects 12
75 CMOS leakage currents 85
76 FinFET 20
77 TCL Cygwin usage basics 20
78 TCL traning overview, Agenda 40
79 Introduction to TCL 58
80 How to run the TCL program 50
81 Formal syntax of the TCL 37
82 set, puts and gets commands 87
83 TCL Operators 58
84 TCL Control statements 63
85 TCL Control statements (if and for statements) 31
86 TCL Control statements (while statements) 30
87 TCL Control statements (switch and foreach statements) 24
88 TCL strings and its operators 68
89 Strings operators Conti... 64
90 Examples of Strings operators Conti... 55
91 Programs on TCL Strings operators 26
92 TCL Lists 55
93 Programs on TCL Lists 61
94 TCL special variables 30
95 Programs on TCL special variables 35
96 Programs on TCL special variables Conti... 54
97 TCL File handling operations 59
98 Programs on TCL File handling operations 56
99 Programs on TCL File handling operations Conti... 82
100 TCL Procedures and Programs on TCL Procedures 50
101 TCL Procedures and Programs on TCL Procedures Conti... 52
102 TCL Procedures and its parameters 47
103 TCL Arrays 47
104 TCL Associative Arrays 33
105 Programs on TCL Arrays 105
106 TCL Dictionary 48
107 TCL Regular expression 48
108 Programs on TCL Regular expression 46
109 Programs on TCL Regular expression Conti... 46
110 Programs on TCL Regular expression Conti... 92
111 PD BASICS SES1 120
112 PD BASICS SES2 167
113 PD BASICS SES3 140
114 PD BASICS SES4 105
115 PD BASICS SES5 132
116 PD BASICS SES6 113
117 PD BASICS SES7 110
118 PD BASICS SES8 70
119 fkf Introduction to digital system 10
120 ASIC Design flow 149
121 Factors affecting delay and Power in CMOS 126
122 Input file - .lib file 106
123 Input file - .lef file 73
124 Input file - .tf and tlu+ file 75
125 Netlist and Hireachial design 90
126 Creating Core area and Die Area 92
127 Port Placement 43
128 TCL Program for Port Placement using Different Commands 98
129 Macros and Type of Macros 121
130 Macro Placement Guide lines 47
131 Blockages and Keepout Margin 31
132 Power Reduction Techniques - Multi Voltage design 37
133 Power Reduction Techniques - Multi Vt Cells 10
134 Power Reduction Techniques - Clock gating Design 14
135 UPF For Multivoltage design 87
136 Power Reduction Techniques - Power gating design 71
137 End cap cells 35
138 TAP cells , TIE Cells DCAP and Spare cells 85
139 Power Planning 92
140 Sanity Checks at each stage and basics of timing 184
141 Setup and Hold Analysis 57
142 In to reg and reg to out path discussion 141
143 PBA and GBA paths 115
144 Timing Exceptions 67
145 Uncertainity , Skew , transition and Driving cell 82
146 Placement goals and checks before placement stage 93
147 Inputs to placement and Placement steps 120
148 Placement Optimization Techniques 189
149 CTS and Clock gating cells 123
150 CTS spec and Clock tree exceptions 98
151 CTS steps and CRPR 141
152 Routing 130
Curriculum

Specification
RTL coding, lint checks
RTL integration
Connectivity checks
Functional Verification
Synthesis & STA
Gate level simulations
Power aware simulations
Placement and Routing
DFT
Custom layout
Post silicon validation
Conductors, Semiconductors, Insulators
Intrinsic and Extrinsic Semiconductors
Diode
BJT
MOSFET (NMOS, PMOS, CMOS)
FinFET
Device Fabrication
Significance of above aspects with Physical Design flow
Shells
File and directory management
User administration
Environment variables
Commonly used commands
Shell scripting basics
SEd and AWK
Revision management
Makefiles
Digital Design basics
combinational logic
sequential logic, FF, latch, counters
Memories
Setup time, Hold time, timing closure, fixing setup time and hold time violations
STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
www.vlsiguru.com/digital-design-complete
Introduction to all the majorly used keywords on PD flow
VLSI Technology concepts
Resistance, Capacitance, Inductance
Parasitic capacitance
L-C-R circuit analysis
RC circuit significance with circuit delay
Clock distribution concepts, skew
Introduce TCL
Why TCL?
TCL Script Processing
Understand TCL uses and strengths
Writing simple TCL scripts
TCL for VLSI scripting
TCL : Main Features
TCL in EDA
TCL shell (tclsh)
Working with TCL scripts (UNIX)
TCL Interpreter in SoC Design Tools
TCL Scripting for SoC Design
TCL Commands
Variables
Substitution and Command Evaluation
Operators
Mathematical Functions
Procedures
Control flow : if, if-else, switch, for, foreach, while, break and continue
string, string operations
List, List manipulation
Arrays, array methods
Working with files
Command line arguments
Regular expressions
Complete TCL Scripts
TCL Packages
Basics of Synthesis
High Level Synthesis Flow
Reading of Verilog RTL File
Target and Link Libraries
Resolving References with Link Libraries
Reading hierarchical Designs
Reading ddc design
Analyse & Elaborate Commands
Constraining and Compiling RTL
Post Synthesis Output Data
Constraining Register to Register Paths
Constraining Inputs Paths
Constraining Outputs Paths
Virtual Clock
Load Budgeting
Default Path Groups
Creating User-defined Path Groups
Prioritizing Path Groups
Timing Reports
Analyzing Timing Reports
Defining a Clock with additional options
Input Delay with additional options
Output Delay with additional options
Pre-CTS versus Post CTS Clock Latencies
Independent IO Latencies
Output Delay with Network Latency
Output Delay with Source Latency
Different IO versus Internal Latencies
IO Clock Latencies
Handling Different IO Vs Internal Latencies
Virtual External Clock Latencies
Included External Clock Latencies
Multiple Synchronous Clocks
Multiple Clocks Input Delay
Maximum Internal Input Delay
Multiple Clock Output Delay
Maximum Internal Output Delay
Inter Clock Uncertainty
Generated Clocks
Mutual Exclusive Synchronous Clocks
Logically Exclusive Clocks
Multiple Clocks per Register
Cross Talk Analysis
Asynchronous Clocks
Multi Cycle Paths and Constraints
High Level Multi-Voltage Design Concepts
Supplies and Power Domains
Power Ports and Nets
Level Shifters
Power States and PS Table
IC Compiler II Library Manager
ICC Compiler II NDM Cell Library
Cell Library Characteristics
Library Manager Flow
Tech Only NDM Library
Technology-Only Library Flow
Technology File
Read TLU+ Files
Tech Library Preparation
Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction
Top Level, Sub-System Level and Block Level Design Setup
Set up initial Design Implementation
Loading Netlist from Synthesis
Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
Flow Setup and Design Setup
Loop-back to Synthesis for Correlation issues correction
Initial Floorplanning settings
Define Pad Instances (Physical Cells)
Pad Instance co-ordinates
Start Floorplaning
Core Die Size setting
Floorplanning of Pad Instances
Pad Filler Insertion
Define Pad Ring Power Grid
Macro Instance constraints
Macro Instance Array creation
Macro Instance Orientation
Anchor based and Relative Placement of Macro Instances
Macro Instance-Channel settings
Macro Instance placement - Manual
Congestion probability around Macro Instances
Defining Placement Blockages
Running placement
Defining placement strategies
In Place Optimization
Hierarchical Placement
Relative Placement
Congestion analysis and reduction
Macro placement changes to reduce congestion
Standard Cell Placement Constraints
Halo creation for instances
Congestion Analysis with Standard Cell placement
Local Congestion Reduction
Density Screen and Placement Blockage for Standard Cells
Congestion Aware Placement
Re-Check Macro Placement for better Congestion relief
Create Balanced Buffer Trees for High Fanout Net
Defining Power Structure
Logical Power/Ground Connections
Setting Power Network Constraints
Create and Analyze Power Structure
Change Power Constraints and Re-Createto meet IR requirements
Power Ground Pin connection and create Power Rails
Power Network Checks for IR and Resistance
Placement Blockage for Power Network
Incremental Placement
Re-Order Scan connectivity within Chain
Re-Partition Scan connectivity across Chains
SCANDEF file based Scan Chain Re-Ordering
Congestion checks for Overflow again
RC extraction for Net Parasitics
Check Timing for Max Analysis
Run Timing/Congestion aware Placement
Logic Re-Structuring for Placement and Timing
Check Pre-CTS timing based on Global Routing and Detailed Placement
Setting Clock Constraints such as Target Skew Target Insertion Delay
Clock Root Attributes as Stop, Float and Exclude Pins
Building for Generated and Gated Clocks
Don't Touch attribute on existing Clock Tree structure
Defining Clock Buffers and Inverters.
Set Clock Tree Timing DRCs.
Non-Default Clock Routing rules setting
Perform Clock Tree Synthesis and Clock Tree Optimization
Reduce Hold Violations in Data paths and Scan Paths
Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
Synchronous Clock Balancing
Cross-Clock Delay Balancing
Logical Hierarchy aware CTS
Max and Min Analysis and subsequent Optimization
Fixing Violations
CTS Optimization across other modes and PVT corners (MMMC)
Skew and Insertion Delay checks
Checking Crosstalk on Clock Network
Pre-Route check points
Routing fundamentals
Global Route
Detail Routing
Track Assignment and Route
Refining Detailed Route
Over the Macro routing
Non-Preferred Routing direction
Clock Net Routing
Initial Data path routing
Redundant VIA insertion setting
Post Detailed Route Optimization
Fixing DRC Violations
Post Detailed Route Delay Calculation Algorithms
Crosstalk Delay and Noise Analysis and Fix
Check Leakage Power Dissipation
VT Cell swap for power and timing trade-off
Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
Reduce Dynamic power
Meet Total Power target
Functional ECO
Timing ECO
Metal Only ECO using Spare Cells for base frozen designs
2 Hands on projects covering detailed flow from Synthesis, input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification
Projects based on multi voltage domain
Student will be working on 3rd project independently with trainer/mentor support.
Antenna Rules and Fixes
Critical Area Analysis
Wire Spreading and widening
Setting minimum metal jog length
Filler Cell Insertion
Metal Fill
Timing Checks after Metal Fill
Parasitic Extraction for SignOff timing analysis
Export Netlist
Export GDSII
Facing interviews effectively
Industry work culture
Group discussions

Benefits of eLearning?
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  • Learn at Your Pace - VLSIGuru eLearning courses are self-paced, so you can proceed when you're ready
Course Instructor
  • Sreenivas Reddy — Founder, VLSIGuru
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Course Highlights

  • 1-1 mentor support
  • Mentor guidance support for assignments
  • Multiple mock interviews
  • Dedicated live support sessions over weekends
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TESTIMONIALS

What Our Students Says About Inskill

ONKAR JOSHI
☆ ☆ ☆ ☆ ☆

I enrolled in Frontend Verification training course, firstly about the syllabus, they teach a lot of things I have compared to other classes no-one teaches so many things as VLSIGURU has taught me. The live lectures happen on regular basis which is a combination of theory as well as practicals. The mentors are just awesome they have a very good knowledge about the modules and clear our every doubts.
The admins are very much co-operative and understandable and help you throughout the course.
The concepts taught are in a very simplified manner and every lecture is recorded.
Very much satisfied will recommend to any VLSI enthusiast

7 Days Ago
Uday G R
☆ ☆ ☆ ☆ ☆

VLSIGURU training institute is one of the best training institute for VLSI domain.
They offer best courses for a very low and affordable prices.
I took e-learning courses, the course content and materials are well planned according to the industry requirements.
Their lectures are very detailed and cover all the concepts.
The projects and assignments they give are helpful in cracking a job.
The admin teams is very supportive all the time. I would definitely recommend to others

10.04.2018
Vinutha M B
☆ ☆ ☆ ☆ ☆

I have taken training at VLSIGURU for Design and functional verification course through online,
where i got more practical knowledge then usual syllabuses.
I was very much satisfied learning at this training institute.
Especially with the way of teaching, they gave individual attention for each and every students and i had a very good experience
which brought me some confidence for facing any trouble to learn any topics they clarify each stages in training period.
every sessions recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provide online access as well.
This institute has highly well experienced real time working professionals as trainers.
thanks to VLSIGURU institute.

5 Month Ago
Beulah Grace
☆ ☆ ☆ ☆ ☆

I have taken training at VLSIGURU for Design and Verification course through online.
They have very experienced faculty with industrial knowledge.
The trainers explained every concept from the very basic to core concepts with good explanation.
Every doubt has been clarified with patience and in detail.
Every session os recorded and can be accessed through their website when required.
The institute also provided hands-on experience with the required tools and provided online access as well.
VLSIGURU institute also provided lab support to solve and get experience with the tool and gain knowledge on core concepts.
Interview preparation sessions has also been conducted along with mock interviews and training sessions.
It is the best institute to gain knowledge in core domain with affordable prices.
I Thank VLSIGURU for helping me to gain knowledge in the core domain.

6 Month Ago

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